This paper presents an analog-assisted hybrid low-dropout regulator (LDO) with a wide load current range and fast transient response. The proposed design is composed of digital and analog loops of which the transient response is dictated by the digital portion. A fast approximation algorithm leveraging charge distribution reduces settling time significantly compared to linear and SAR approaches. A wide load range droop detector further improves transient response with negligible power overhead. The analog assisted circuits continuously provide current in response to the load current change without disturbing the loop dynamic. Implemented in a TSMC 180-nm standard CMOS technology, the LDO supports a 430 mA maximum load and ensures loop stability without external capacitors. It achieves a 480 mV undershoot at 430 mA with 100 ns edge time,$49~\mu $A quiescent current, and settling times of 225 ns and 260 ns for undershoot and overshoot at$C_{L}=0$pF when a 10-MHz clock is used. Measurement shows that activating the droop detector reduces undershoot by 54%.

This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement technique dividing the loop dynamic into three phases in which the current regulation circuits (CRC), large-signal derivative path control circuits addressing the design challenge of slew rate limitation, and the hybrid passive-active frequency compensation (PAFC) for small signal settling time improvements are introduced lends the proposed LDO to providing constant output voltage under the condition of large load variations. The LDO is designed in TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm2 active area. The quiescent current is 380$\mu \mathrm{A}$at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6$\mu \mathrm{s}, 4.5\mu \mathrm{s}$, and 9.8$\mu \mathrm{s}$, respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.

This paper presents the principle, design, and analysis of a bi-directional gated ring oscillator (BDGRO) time integrator for time-based signal processing. The time integrator features full compatibility with technology, rapid integration, low power consumption, a virtually unlimited dynamic range, built-in dynamic element matching, and self-digitization. A detailed analysis of the impact of the imperfections of the time integrator including nonlinearity, skew, supply voltage noise, device noise, and metastability-induced gating errors is provided, supported with simulation results. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Virtuoso/Spectre with BSIM3 device models. Time integration is confirmed using simulation results in both time and frequency domains. The time integrator exhibits a clean spectrum without noticeable harmonics and consumes 0.25 mW with a gain of 15.48 dB at 20 MS/s.

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

An 8-bit time-mode successive approximation register time-to-digital converter (SAR TDC) is proposed. The TDC achieves a high resolution and a better power/area efficiency by using a pre-skewed delay line with digital time interpolation. The impact of pre-skewing on delay and power consumption is investigated. A cascode inverter interpolation cell with improved input-output isolation is introduced. The impact of the slope of input signals on the linearity of the time interpolator is investigated. Timing errors caused by device noise are quantified. The SAR TDC is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the SAR TDC operated at 10 MS/s achieves 0.33 ps solution, 9.68 ENOB, and 0.20 pJ/conv. FOM.

Recently a method was proposed to determine the parameters for each Class DE driver in high-intensity focused ultrasound (HIFU) arrays for efficient operation and to compensate for variations in the impedance of each array element. This work extends that method to consider the effect of switch resistance and to provide limited control on the power delivered to the transducers with a constant supply voltage while keeping a good efficiency. The method is experimentally validated using an integrated driver developed by the authors. This paper also shows that the frequency range for efficient electrical operation is close to the frequency where the transducer array presents a peak in the conversion efficiency.

This paper proposes a charge-domain quadrature down-conversion sampling mixer with improved filter functionality. An 4-path bandpass filter and a quadrature sampling mixer are integrated in a cascode architecture to minimize power consumption while providing a degree of programmability. The proposed design is applicable to heterodyne receivers for suppressing aliasing signals, large out-of-band blockers, and IF images. It also offers partial channel selection. Designed in IBM 130 nm 1.2V CMOS technology, simulation results from Spectre of Cadence Design Systems with BSIM4 device models demonstrate that the proposed design exhibits aliasing rejection of 70 dB, stop band attenuation of 60 dB while consuming current of 104μ A.