Resistive RAM (RRAM) design optimization and reliability monitoring is essential not only to gain market share in the highly competitive emerging memory sector, but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. Common problems with RRAM are related to high variability in operating conditions and low yield. Although research has taken steps to resolve these issues, variability remains a major hurdle for the wide spread of the technology. In this paper, a novel test structure consisting of an array of non-addressable IT-IR RRAM memory cells with parallel connection of all memory elements is introduced. The test structure can be used as a powerful tool for process variation monitoring during a new process technology introduction and also for marginal cell populations detection during process maturity. The test structure is designed to measure RRAM parameters of interest based on a simple measurement methodology: from the transfer characteristic measured under the select transistor clamping bias, it is possible to obtain accurate information on the RRAM switching parameters as well as the ON/OFF resistance values.

Multi-Level Cell (MLC) technology can greatly reduce Resistive RAM (RRAM) die sizes to achieve a breakthrough in cost structure. In this paper, a novel design scheme is proposed to realize reliable and uniform MLC RRAM operation without the need of any read verification. MLC is implemented based on a strict control of the cell programming currents of 1T-1R HfO2-based RRAM cells. Specifically, a self-adaptive write termination circuit is proposed to control the RRAM RESET current. Eight different resistance states are obtained by varying the compliance current which is defined as the minimal current allowed by the termination circuit in the RESET direction.

Today computing centric von Neumann architectures face strong limitations in the data-intensive context of numerous applications, such as deep learning. One of these limitations corresponds to the well known von Neumann bottleneck. To overcome this bottleneck, the concepts of In-Memory Computing (IMC) and Near-Memory Computing (NMC) have been proposed. IMC solutions based on volatile memories, such as SRAM and DRAM, with nearly infinite endurance, solve only partially the data transfer problem from the Storage Class Memory (SCM). Computing in SCM is extremely limited by the intrinsic poor endurance of the Non-Volatile Memory (NVM) technologies. In this paper, we propose to take the best of both solutions, by introducing a Computing Row Buffer (C-RB), using a Computing SRAM (C-SRAM) model, in place of the standard Row Buffer (RB) in the SCM. The principle is to keep operations on large vectors in the C-RB of the SCM, minimizing data movement to and from the CPU, thus drastically reducing energy consumption of the overall system. To evaluate the proposed architecture, we use an instruction accurate platform based on Intel Pin software. Pin instruments run time binaries in order to get applications' full memory traces of our solution. We achieve energy reduction up to 7.9x on average and up to 45x for the best case and speedup up to 3.8x on average and up to 13x for the best case, and a reduction of write accesses in the SCM up to 18 %, compared to SIMD 512-bit architecture.

The development of non-conventional Von-Neumann architectures becomes essential for breakthrough computing in Internet of Things (IoT) devices. The main objective for IoT application is to lower as much as possible the power consumption to promote autonomy. The key to solve this challenge is to reduce the data transfer between memory and computing unit. As emerging non-volatile memories and especially resistive switching technologies (ReRAM) can today be co-integrated with CMOS on hybrid process, we propose in this paper to develop bitwise logic operations inside and close to the memory array. Using two transistors - one ReRAM (2T1R) memory cell architecture with differential approach to enhanced read reliability, we can perform logic operations without impacting the global memory architecture. Thanks to parallel data sensing, the structure enables fast computation of any bitwise logic operations (ID, AND, OR, XOR in their natural or complementary form) with high reliability, promoting the computing in memory (CiM) concept.

In human crowds as well as in many animal societies, local interactions among individuals often give rise to self-organized collective organizations that offer functional benefits to the group. For instance, flows of pedestrians moving in opposite directions spontaneously segregate into lanes of uniform walking directions. This phenomenon is often referred to as a smart collective pattern, as it increases the traffic efficiency with no need of external control. However, the functional benefits of this emergent organization have never been experimentally measured, and the underlying behavioral mechanisms are poorly understood. In this work, we have studied this phenomenon under controlled laboratory conditions. We found that the traffic segregation exhibits structural instabilities characterized by the alternation of organized and disorganized states, where the lifetime of well-organized clusters of pedestrians follow a stretched exponential relaxation process. Further analysis show that the inter-pedestrian variability of comfortable walking speeds is a key variable at the origin of the observed traffic perturbations. We show that the collective benefit of the emerging pattern is maximized when all pedestrians walk at the average speed of the group. In practice, however, local interactions between slow- and fast-walking pedestrians trigger global breakdowns of organization, which reduce the collective and the individual payoff provided by the traffic segregation. This work is a step ahead toward the understanding of traffic self-organization in crowds, which turns out to be modulated by complex behavioral mechanisms that do not always maximize the group's benefits. The quantitative understanding of crowd behaviors opens the way for designing bottom-up management strategies bound to promote the emergence of efficient collective behaviors in crowds.