The ever-increasing computational load and shrinking power budget have accentuated the need for energy-efficient operation of edge devices. In this article, a combination of static CMOS logic and Hybrid Pass transistor logic with Static CMOS output (HPSC), which has no floating or weak nodes and is thus as robust to noise as static CMOS logic, is used for designing toolchain-compatible super-Vth standard cells. Optimized HPSC variants of a 2/3-input XOR cell, a 2/3-input XNR cell, a half adder cell, a full adder cell, and two variants of a 1-bit multiply-accumulate combinational cell are presented in a commercial 65nm Low-Power CMOS technology. Measurements of test structures based on ring oscillators and dummy path techniques show an average frequency and average energy-delay product improvement of up to 30.3% and 32.5% respectively at typical conditions. The proposed cells’ superior performance compared to the commercially available standard cells is also highlighted in terms of propagation delay, leakage, and dynamic power consumption. This shows a promising approach for foundries or other commercial entities to improve digital design performance to about half a technology node at no additional cost.

In this paper, the CMOS inverter chain buffer is optimized for N-path filter switch drivers in a technology-agnostic way. Figures-of-merit are proposed to minimize jitter for minimal power dissipation with consideration of rise/fall-time. Using these, mathematical models are derived based on a simple circuit model and expressed for optimization as a function of the technology-specific inverter output/input capacitance ratio, the number of inverters, and their taper factors. This enables finding designs with any set of taper factors that have lower jitter than common designs for the same power dissipation by sweeping many designs orders of magnitude faster than using circuit simulations. Additionally, analytical equations are derived to quickly allow a designer to find the optimal number and sizing of inverters for the constant and exponential taper designs, either of which is shown to be near-optimal depending on the set of specifications.

High performance and energy efficiency are very crucial aspects in e.g. the field of edge computing where a tight power budget constrains the device operation. Different logic families were explored over the years to design standard cells with higher performance and/or lower power while keeping the noise immunity and the compatibility with design automation tools intact. Hybrid pass transistor logic with static CMOS output (HPSC) seems to be promising and is exploited in this paper to design low energy, high performance and toolchain-compatible standard cells without compromising on noise immunity and chip area. This paper presents a 2/3-input XOR cell, a 2/3-input XNOR cell, two variants of a half adder cell, a full adder cell and two variants of a 1-bit multiply-accumulate combinational cell based on a combination of HPSC and static CMOS logic in a commercial 65nm Low-Power CMOS technology. Post-layout simulations over all the process-voltage-temperature corners show a 4.7% - 35.7% lower energy-delay product with significant improvement in the propagation delay of the proposed cells.

Voice Activity Detection (VAD) is a technique used to identify the presence of human voice in an audio signal. It is implemented as an always-on component in most speech processing applications. As speech is absent most of the time, this component typically dominates the overall average power consumption of the system (excluding microphone). The widespread usage in speech applications and the need for ultra low power VAD have led to a plethora of algorithms and implementations in the hardware domain, necessitating a comprehensive study and analysis to understand (real-time) requirements, different design parameters, testing strategies, but also to identify design trends, challenges and guidelines for future implementations and testing of VAD devices. A scoping review was conducted to identify the articles for hardware implementations of VAD from January 2010 - December 2021, the results of which are presented in this article. The results highlight a big design space being used for VAD along with a lack of standard testing methodology and usage of application-dependent performance metrics. An increased usage of filter-based feature extractors along with neural-network-based classifiers is observed. Due to lack of standardisation, no other trends can be established from the results. A set of rules and guidelines are therefore provided to facilitate the future development and benchmarking of VADs.

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed.

Cross-correlation can be used in energy detection applications, such as spectrum analyzers, but also frequency shift keying (FSK) receivers, to improve noise suppression. To achieve higher signal-to-noise ratio (SNR), integration in time may be used, but could make it rather slow for communication purposes. In order to achieve better data-rates in low SNR conditions, we propose to use multiple chains instead of the traditional two chains. In this paper, we show an analysis of the SNR improvement and the power consumption penalty for BFSK modulation when using more chains. It shows that for low noise correlation between the chains, the improvement in sensitivity is proportional to the number of chains. Also, we develop a figure-of-merit to evaluate the optimum number of chains for different parameters of the receiver design. Furthermore, two examples from literature are analyzed. At their optimum number of chains, they both show ~6dB improvement in sensitivity with similar or even better figure-of- merit.

Spectrum sensing is one of the key characteristics of a cognitive radio. Energy detection provides maximum flexibility by not relying on any prior knowledge, but suffers from an SNR-wall due to noise uncertainty. Crosscorrelation of the outputs of two receiver paths is a technique to reduce the noise level of the total receiver, and hence improves the SNR. The reduction of the noise is limited by correlated noise originating from shared components near the antenna. In this paper we explore the use of a separate antenna for each receiver for crosscorrelation spectrum sensing. One immediate advantage is that due to the removal of the splitter, which was necessary to interface the single antenna to two receivers, the SNR improves, significantly reducing the required measurement time. A lot of the noise correlation can be removed, leading to a lower residual noise floor. The noise at each antenna will still be partially correlated due to mutual coupling, spatial noise correlation and man-made noise. We show that some signal power can be lost in the sensing process due to partial decorrelation of the signal at the two antennas. Fortunately, this seems to be a problem only in highly mobile environments, which makes the use of two-antenna crosscorrelation spectrum sensing an interesting solution towards more reliable energy detection.