FML, a high-level function modelling language developed and used at Bell-Northern Research (BNR), is described in terms of its features, structure, timing capability and manner of execution. The language is presented, not in its full syntactic details, but by way of more helpful illustrations and examples. FML is fully integrated with BNR's functional simulator, FUNSIM, and thereby allows accurate timing and concurrent fault simulation. FML is a register level language with sub-register scheduling and tolerance timing, and it features an efficient mechanism for unknown state processing. To the user, FML is a circuit-designer-oriented, highly readable, easily applied design tool for both IC and PCB design.

Digital simulators are becoming a standard and necessary CAD tool in the circuit design process. The acceptance of this design aid is a result of a number of factors, the predominant one being the over-whelming size and complexity of present day logic circuits and the requirement that a complete test plan be developed for these circuits. Another factor is that recent generation logic simulators have proven to be very flexible tools, capable of simulating very large circuits with a high degree of precision.