An algorithm is presented in which a computer is visually shown a sequence of views of a solid planar object as the object is rotated in space. The computer automatically forms a three-dimensional description of the object. The description consists of a deterministic description of the object's surfaces and how they are interconnected to form the object, along with a measure of each surface's shape which is invariant to three-dimensional rotation. From this self-learned model of the object, the object can later be recognized from any viewing angle. The basis of the algorithm is the ability of the program to determine in a specific visual view: "What do I see now that I have seen before?" This is accomplished by generating two sets of mappings of one object description to another object description.

This paper introduces procedures which enable one to settle the tessellation problem for the class of combinational cellular arrays with each cell having a binary horizontal input and a binary vertical input. Where all input combinations are applicable to all cells in the array in this class, the necessary number of tests is obtained from necessary prime as well as composite tessellations.

In this paper we study feedback in sequential machines that are implemented with trigger or set-reset flip-flop memory elements. A method is given for determining when a machine can be implemented with either trigger or set-reset flip-flop memory elements where the feedback in the machine is given by a Boolean function f. Several results are presented that compare the feedback when a machine is implemented with different memory elements. It is shown that if a sequential machine can be implemented with unit delay memory elements with feedback function f, then it can be realized with set-reset flip-flop with the same feedback function f. For completely specified machines, it is shown that if a machine implemented with trigger flip-flop has no feedback, then the some machine implemented with unit delays will have feedback. Conversely, if an implementation with unit delays has no feedback, then an implementation with trigger flip-flops will have feedback.

Hartmanis and Stearns defined the concept of an inessential error in their study of errors in sequential machines and represented such errors by means of an error partition Π E. Although they showed that ΠE could not be determined using only the usual partition pair algebras, they did not provide a means by which it could be determined. The purpose of this note is to develop an algorithm for the determination of ΠE for a given machine.

The state assignment problem for finite-state sequential machines is examined in the context of threshold logic. An algorithm is developed for assigning binary codes to the states, inputs, and outputs so that the state variable and output variable functions satisfy the necessary condition of 2-assumability that they be linearly separable. The algorithm deals with 2-block partitions by which the assignments are made. First those partitions which cannot be used are computed. For each of the remaining partitions, a list is compiled of those partitions of which one must be used if the given partition is used. Finally, a method is given for constructing the sets of partitions satisfying these constraints and having zero product. Code assignments made by these partition sets will induce 2-asummable functions.

Abstract—In this paper, methods are presented for designing error-correcting capabilities into threshold gate networks so that the logic gates themselves will correct errors of other gates in the network . In all but one of these methods, a given realization is modified by the addition of redundant gates to obtain an error-correcting network . Realizations are obtained by the first three methods which require that an error of any given number of gates be corrected by the gates immediately following those which are in error. This is the multiplexed realization. In the remaining methods, this requirement is replaced by the requirement that a given number of errors be corrected by some gates in the network. Errors of the output gate are not corrected. The last section discusses a method for obtaining an error-correcting network directly from the Boolean function to be realized.

Abstract—This paper is concerned with the study of logic hazards in threshold gate networks. Eichelberger has proved that logic hazards are not present in a sum-of-product (product-of-sum) realization which realizes all of the 1(0) prime implicants of the given Boolean function.[2]Logic gates of the AND or NOR (OR or NAND) variety realize single l(0) prime implicants; therefore, a gate is required for each 1(0) prime implicant to be realized, and the problem of eliminating logic hazards is straightforward.

Assume that our technology uses "black boxes" that may be described by a planar figure. (See Fig. 1.) Each "box" has a finite number of inputs ordered in the manner shown in Fig. 1, from top to bottom on the left-hand side of the "box," and one output coming out of the right-hand side of the "box." The output is some function of the input variables. For the purpose of our discussion, the variables may be continuous or discrete or of any nature whatsoever, and each "box" may have any number of inputs.

During the past few years there has been a considerable amount of literature concerned with the realization of threshold logic. However, there are a number of questions concerning such factors as sensitivity and component savings which cannot be completely answered by such theoretical studies. DONUT (Digitally Operated Network Using Thresholds) is a small general purpose digital computer which was designed and constructed to evaluate the feasibility of using threshold gates as the basic logical element. Exclusive of memory the computer consists of about 500 threshold gates. The design was carried out for five different values of component tolerances and the tightest tolerance version was constructed. Component savings for the constructed machine are about a factor of four compared with the loosest tolerance NOR gate realization. Experiments were made to verify that the power supply and logical voltages were within tolerances in the system environment.

One engineering parameter of importance in the realization of threshold gate networks is the tolerance which must be placed on the coefficients and threshold of the individual components. A previous paper gives a realization procedure which allows this tolerance to be controlled. The present paper gives an alternate realization procedure which also allows the tolerance to be controlled, but which is somewhat different in its application. The new procedure can be considered to be a generalization of an earlier procedure for the single-element realization problem. The function is first decomposed using a generalization of the function tree and then reconstructed using a generalization of the range theorem plus some additional simplification theorems.

In the realization of a logical function by a network of threshold components, one important engineering parameter is the tolerances which must be placed on the coefficients and threshold of the individual components. For threshold gates in which the logical ``zero'' corresponds to a constant signal of zero value and in which the coefficients are all positive or all negative, these tolerances are functions only of the gap boundaries of the map realized by the component. A set of theorems is presented that define ``algebraic-like'' operations which provide a means for performing a sequence of symbolic operations on the desired logical function whereby the latter is transformed into a description of a network of threshold components which is its realization. Using these theorems a procedure is given for realizing an arbitrary logical function as a network of threshold components with specified sensitivity.

A previous paper gives a procedure for the testing and realization of linearly-separable switching functions, i.e., functions which can be realized by a single threshold component. That procedure can be considerably simplified, particularly when the given function is symmetric in sets of two or more variables. The simplifications arise due to a reduction of the number of functions in the function tree in view of the coefficient ordering. Although this procedure was derived with the aim of reducing the amount of computation below that required for straightforward solution of the simultaneous inequalities that define the problem, the resulting method has some interesting relationships to that due to Winder.