Reduced attentional capacity caused by increased mental workload (MWL) among drivers can cause traffic accidents. Against this background, a method for effective MWL evaluation is required. The proposed method is used to map multidimensional biological signals into a probabilistic space based on a mixed normal distribution model. The load state of the driver is evaluated, and the cognitive load can be determined from a posteriori probability. In the experiments reported here, tasks performed to examine tracking of the vehicle in front and N-Back evaluation helped to clarify the cognitive load of the three subjects, for whom multidimensional biosignal monitoring was performed. The results demonstrated a high correlation between evaluation and NASA-TLX values. In other experiments, increased evaluation values were observed in satnav operation. Accordingly, the proposed method is considered suitable for real-time driver MWL evaluation.

A scalable network with high bisection bandwidth and high availability requires efficient use of the multiple paths between pairs of end hosts. OpenFlow is an innovative technology and enables fine-grained, flow level control of Ethernet switching. However, the flow table structure defined by OpenFlow is not hardware friendly and the scalability is limited by the switch device. OpenFlow is also not sufficient for fast multipath failover. To overcome these limitations, we propose DomainFlow in which the network is split into sections and exact matches are used where possible to enable practical flow management using OpenFlow for commodity switches. We applied a prototype of DomainFlow to multipath flow management in the Virtual eXtensible LAN (VXLAN) overlay network environment. The total number of flow entries was reduced to 1/128 using currently available commodity switches, which was not possible before.

Formal verification, especially error detection, is rapidly increasing in importance with the rising complexity of designs. The main constraint in verification is the total amount of resources available - both time as well as memory. Most attempts at verification only use a single processor. Recently, various attempts have been made to use parallel and distributed methods for verification. However, verification in a Grid-based environment has not yet been very widely adopted. As personal computers gain in computing capacity, the concept of computation grids is gaining acceptance. Here, a grid is a network of machines that may not be dedicated to a specific computational use, but may only be available some of the time. This is a unique environment where massive parallelism is possible by using otherwise idle CPU cycles from a large number of computers. Such processors may even be in geographically diverse locations. We describe a Grid-based verifi- cation environment for detecting errors in a design. We verify user-written assertions as well as properties, e.g. unreachable code, index-out-of-range, that are extracted automatically from the design using a state-of-the-art HDL parser. Such an approach can help the user to quickly find RTL level bugs earlier in the design cycle.

Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verification is to define good verification scopes; we should define clearly what to be verified formally upon designs under test. We considered the following three practical requirements when we defined the scope of formal verification. It should be: (a) hard to verify; (b) small to handle; and (c) easy to understand. Our novel approach is to break down generic properties for the system into stereotype properties in block level and to define requirements for Verifiable RTL. Consequently, each designer instead of verification experts can describe properties of the design easily, and formal model checking can be applied systematically and thoroughly to all the leaf modules. During the development of a component chip for server platforms, we focused on RAS (reliability availability and serviceability) features and described more than 2000 properties in PSL. As a result of the formal verification, we found several critical logic bugs in a short time with limited resources, and successfully verified all of them. This paper presents a study of the functional verification methodology.

This paper presents HAL's Mercury Interconnect Architecture, an interconnect infrastructure designed to link commodity microprocessors, memory, and I/O components into high-performance multiprocessing servers. Both shared-memory and message-passing systems, as well as hybrid systems are supported by the interconnect. The key attributes of the Mercury Interconnect Architecture are: low latency, high bandwidth, a modular and flexible design, reliability/availability/serviceability (RAS) features, and a simplicity that enables very cost-effective implementations. The first implementation of the architecture links multiple 4-processor Pentium™ Pro based nodes. In a 4-node (16-processor) shared-memory configuration, this system achieves a remote read latency of just over 1 µs, and a maximum interconnect bandwidth of 6.4 GByte/s. Both of these parameters far outpace comparable SCI-based solutions, while utilizing much fewer hardware components.