As transistor sizes continue shrinking, impacts of variability has become ever more paramount in circuit design and manufacturing. Their accurate representations in model cards help save design margins and provide appropriate guidelines in design technology co-optimization (DTCO). To address such a challenge, we propose a novel machine learning framework, Normalizing Flow-Based Joint Generative Model (NFGen), which generates a comprehensive model library from a limited number of model cards. Unlike traditional generative methods that focus on the marginal distribution of model card parameters, NFGen is the first model to approximate their joint distribution, which includes information on their correlation and thus enables closer representation of variability effects. In addition, we introduce two similarity metrics to rigorously evaluate the quality of generated model cards. Experimental results show that NFGen reduces overall error by 2x to 8x compared to state-of-the-art methods, validating its superiority in variability-aware DTCO.

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on the tradeoff between performance, stability, and power efficiency. In addition to size optimization, physical model parameters including CNT density, CNT diameter, and CNFET flat band voltage are evaluated and optimized for CNFET SRAM performance improvement. Optimized CNFET SRAM is compared with state-of-the-art 7-nm FinFET SRAM cell based on Arizona State University [ASAP 7-nm FinFET predictive technology models (PTM)] library. We find that the read, write EDPs, and static power of the proposed CNFET SRAM cell are improved by 67.6%, 71.5%, and 43.6%, respectively, compared with the FinFET SRAM cell, with slightly better stability. CNT interconnects both inside and in-between CNFET SRAM cells are considered to compose an all-carbon-based SRAM (ACS) array which will be discussed in the Part II of this article. A 7-nm FinFET SRAM cell with copper interconnects is implemented and used for comparison.

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of$0.28\times $,$0.52\times $, and$0.76\times $respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.

This article is a review of the current progress and results obtained in the European H2020 CONNECT project. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, 2) modeling and simulation from atomistic to circuit-level bench-marking and performance prediction, and 3) characterization and electrical measurements. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a review and informative cornerstone on carbon nanotube interconnects.

Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: 1) non-Gaussian distributions and 2) highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multidimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.

In this paper we will present integrated time dependent variability tool flow that links statistical TCAD simulations, statistical compact model extraction and statistical circuit simulation. This allows the concepts of Design-Technology Co-Optimization (DTCO) to be extended into the reliability domain. The simulations are based on Gold Standard Simulations' (GSS) 3-D Kinetic Monte Carlo TCAD technology, which enables the simulation and analysis of the trapping/de-trapping history of large ensembles of microscopically different transistors. The results of the physical simulation are than captured in accurate time dependent statistical compact models. As a result, accurate statistical circuit simulation can trace the statistical impact of the degradation on the functionality of the underlying circuits and systems.

Summary form only given. This paper describes the fully automated GSS tool flow, which bridges the gap between Technology Computer Aided Design (TCAD) at the transistor level, and circuit simulations and verification. The purpose of the tool flow is twofold: (i) to allow rapid simulation-based Design-Technology Co-Optimisation (DTCO) and (ii) to allow generation of accurate compact models for Preliminary Design Kit (PDK) development at the early stages of new technology development. The aim is to capture accurately process, statistical and time dependent variability in the DTCO and early PDKs. The operation of the automated tool flow is exemplified in the comprehensive PDK compact model development for a 14 nm SOI FinFET process, and the corresponding transistor / SRAM cell co-optimisation.

In this paper we highlight the important role of full-scale 3D Ensemble Monte Carlo (EMC) transport simulations in the performance analysis of contemporary and future decananometer MOSFETs. Considering both electron and hole transport in alternative device structures and materials we demonstrate that conventional drift diffusion (DD) simulations using standard mobility models fail to capture the non-equilibrium transport effects present in these devices, limiting their effectiveness in terms of performing predictive simulation of Si based FinFETs. We clearly demonstrate the capabilities and the power of EMC in evaluating the scaling potential and performance of FinFETs and quantum well transistors employing high mobility materials and the impact that additional scattering sources has on their performance.

We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, which enables TCAD-based transistor-cell co-design and path finding during the early phase of a technology node.

A set of analytical models based on the Pearson distribution function applied to the modeling of ion implantations in the 3-D structure of FinFETs is presented. The method provides a succinct way to simulate the doping profiles in FinFETs at low computational cost. Compared to previous analytical methods based on Gaussian distributions, this approach handles more realistic asymmetrical doping distributions arising from ion implantation. A simulation module in C++ has been developed to model ion implantations in FinFETs based on this analytical approach. The simulation module is demonstrated in an example simulation of a silicon-on-insulator FinFET with physical gate length of 20 nm.

Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.

This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET at 25, 18 and 13nm nodes are calibrated by a 3D atomistic device simulator with chip measurements of 35nm gate length devices. Synthesis results confirm that the variability of circuit performance will increase as device scaling continues, and can be more severe in new circuits at 18nm than in those stressed for a period of three years at 35nm. In addition, the results also reveal that increasing power consumption as adopted in adaptive supply voltage (ASV) and adaptive back bias (ABB) schemes is not a sustainable solution to compensate the drift in performance for future generations of CMOS circuits and systems.

Quantitative simulations of the statistical impact of negative-bias-temperature-instability (NBTI) on pMOSFETs, and positive-bias-temperature-instability (PBTI) on nMOSFETs are carried out for a 45nm low power technology generation. Based on the statistical simulation results, we investigate the impact of NBTI and PBTI on the degradation of the static noise margin (SNM) of SRAM cells. The results indicate that SNM degradation due only to NBTI follows a different evolution pattern compared with the impact of simultaneous NBTI and PBTI degradation.

The scaling of MOSFETs has improved performance and lowered the cost per function of CMOS integrated circuits and systems over the last 40 years, but devices are subject to increasing amounts of statistical variability within the deca-nano domain. The causes of these statistical variations and their effects on device performance have been extensively studied, but there have been few systematic studies of their impact on circuit performance. This paper describes a method for modelling the impact of random intra-die statistical variations on digital circuit timing and power consumption. The method allows the variation modelled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterisation tools. The method provides circuit designers with the information required to analyse power, performance and yield trade-offs when fabricating a design, while removing the large levels of pessimism generated by traditional Corner Based Analysis.

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated ID-VGcharacteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data.

Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical circuit simulations.

Static statistical variability and time-dependent reliability are traditionally analyzed separately. This paper presents a new methodology which combines both types of variability within a single circuit analysis framework. A comprehensive Negative Bias Temperature Instability (NBTI) model was implemented. Effects of random discrete dopants, line edge roughness and poly-Silicon granularity were considered. Using a 74X-series benchmark circuit (4-bit fast-carry adder) as an example, the concept of integrating both static statistical variability and time-dependent reliability into circuit analysis is demonstrated.

In this paper we study the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of an inverter at the 45 nm technology generation using statistical circuit simulation. The impact of the variability on switching trajectories and propagation delay are studied using an inverter chain with differing Fan-Out/Fan-In (FO/FI) ratios.

The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of 'atomic-scale' transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner.

The UK Engineering and Physical Sciences Research Council (EPSRC) funded project ¿Meeting the Design Challenges of nanoCMOS Electronics¿ (nanoCMOS) is developing a research infrastructure for collaborative electronics research across multiple institutions in the UK with especially strong industrial and commercial involvement. Unlike other domains, the electronics industry is driven by the necessity of protecting the intellectual property of the data, designs and software associated with next generation electronics devices and therefore requires fine-grained security. Similarly, the project also demands seamless access to large scale high performance compute resources for atomic scale device simulations and the capability to manage the hundreds of thousands of files and the metadata associated with these simulations. Within this context, the project has explored a wide range of authentication and authorization infrastructures facilitating compute resource access and providing fine-grained security over numerous distributed file stores and files. We conclude that no single security solution meets the needs of the project. This paper describes the experiences of applying X.509-based certificates and public key infrastructures, VOMS, PERMIS, Kerberos and the Internet2 Shibboleth technologies for nanoCMOS security. We outline how we are integrating these solutions to provide a complete end-to-end security framework meeting the demands of the nanoCMOS electronics domain.

The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of individual atoms will affect their behaviour. This will cause the transistors on a chip to have highly variable characteristics, which in turn will impact circuit and system design tools. The EPSRC project "Meeting the Design Challenges of Nano-CMOS Electronics" (Nano-CMOS) has been funded to explore this area. In this paper, we describe the distributed data-management and computing framework under development within Nano-CMOS. A key aspect of this framework is the need for robust and reliable security mechanisms that support distributed electronics design groups who wish to collaborate by sharing designs, simulations, workflows, datasets and computation resources. This paper presents the system design, and an early prototype of the project which has been useful in helping us to understand the benefits of such a grid infrastructure. In particular, we also present two typical use cases: user authentication, and execution of large-scale device simulations.

In this paper we review the major sources of variability in CMOS devices corresponding to the 45nm technology node and beyond. The focus is on intrinsic parameter fluctuations introduced by discreteness of charge and matter, which play an increasingly important role in the present and future CMOS devices and cannot be controlled or reduced by tightening the process tolerances.

We present a hierarchical approach to the "atomistic" simulation of aggressively scaled sub-0.1-/spl mu/m MOSFETs. These devices are so small that their characteristics depend on the precise location of dopant atoms within them, not just on their average density. A full-scale three-dimensional drift-diffusion atomistic simulation approach is first described and used to verify more economical, but restricted, options. To reduce processor time and memory requirements at high drain voltage, we have developed a self-consistent option based on a solution of the current continuity equation restricted to a thin slab of the channel. This is coupled to the solution of the Poisson equation in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison to the full self-consistent solution. At low drain voltage, a single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. In this case, the current is calculated by solving the current continuity equation in a drift approximation only, also in a thin slab containing the MOSFET channel. The regions of applicability for the different components of this hierarchical approach are illustrated in example simulations covering the random dopant-induced threshold voltage fluctuations, threshold voltage lowering, threshold voltage asymmetry, and drain current fluctuations.