The project VE-FIDES will contribute with a solution based on an innovative multi-level fingerprinting approach to secure electronics supply chains against the threats of malicious modification, piracy, and counterfeiting. Hardware-fingerprints are derived from minuscule, unavoidable process variations using the technology of Physical Unclonable Functions (PUFs). The derived fingerprints are processed to a system fingerprint enabling unique identification, not only of single components but also on PCB level. With the proposed concept, we show how the system fingerprint can enhance the trustworthiness of the overall system. For this purpose, the complete system including tiny sensors, a Secure Element and its interface to the application is considered in VE-FIDES. New insights into methodologies to derive component and system fingerprints are gained. These techniques for the verification of system integrity are complemented by methods for preventing reverse engineering. Two application scenarios are in the focus of VE-FIDES: Industrial control systems and an automotive use case are considered, giving insights to a wide spectrum of requirements for products built from components provided by international supply chains.

This paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. The results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

Physical Unclonable Functions (PUFs) derive un-predictable and device-specific responses from uncontrollable manufacturing variations. While most of the PUFs provide only one response bit per PUF cell, deriving more bits such as a symbol from a higher-order alphabet would make PUF designs more efficient. This type of PUFs is thus suggested in some applications and subject to current research. However, only few methods are available to analyze the statistical performance of such higher-order alphabet PUFs. This work, therefore, introduces various novel schemes. Unlike previous works, the new approaches involve statistical hypothesis testing. This facilitates more refined and statistically significant statements about the PUF regarding bias effects. We utilize real-world PUF data to illustrate the capabilities of the tests. In comparison to state-of-the-art approaches, our methods indeed capture more aspects of bias. Overall, this work is a step towards an improved quality control of higher-order alphabet PUFs.

Physical Unclonable Functions (PUFs) leverage manufacturing variations to generate device-specific keys during runtime only, overcoming the need for protection after power-off as for Non-Volatile Memory. The main challenges of PUF-based key storage are reliability of the response and sensitivity to Side-Channel Analysis (SCA). Oscillator-based PUFs are particularly sensitive to frequency spectrum SCA. Existing countermeasures can protect sign-based bit derivation that requires error correction or discarding unreliable bits to achieve reliable key generation. Amplitude-based bit derivation enhances the reliability of oscillator-based PUFs without discarding unsteady response bits, keeping a high entropy. However, existing lightweight countermeasures against SCA are not applicable for this case. This raises the demand for an alternative solution. This work targets the protection of amplitude-based bit derivation combined with the Loop PUF, an oscillator-based PUF primitive well suited for key generation. It presents the Interleaved Challenge Loop PUF (ICLooPUF), a side-channel-hardened offspring of the Loop PUF that uses dynamic challenge interleaving. The SCA-protected PUF primitive is applicable to amplitude-based and sign-based bit derivation methods, and requires a low hardware overhead. Theoretical and experimental results show the efficiency of the protection mechanism.

Microprobing is applied to intercept data from on-chip signals, such as data passing through a data bus. Hence, it allows for extracting a full dump of this data, e.g., the firmware of a microcontroller, cryptographic key material, or any other type of passing data on the physical metal lines and/or the physical cells of the data bus connected to the metal lines. It is categorized as an invasive and physical attack vector against which software measures are insufficient for protection. As a countermeasure detecting microprobing attacks and enabling appropriate protection mechanisms, we propose a new probing detector for an industrial sub-40-nm advanced process node. It is based on ring oscillators (ROs), which are formed from the data bus lines. The oscillation frequency, caused by the capacity of bus lines, is measured and compared to detect any attached microprobes. The concept is optimized for detection of placed microprobes on both regular and irregular data buses or on any other pair of lines. For this purpose, a statistics-driven decision is made to distinguish probed from not probed lines. To improve the concept for high capacitance irregular lines, a hybrid design and test time calibration is proposed and analyzed, which shows the applicability of the concept under irregular bus lines, local variations, and jittery conditions. The results show that the approach results in low false positive (FP) and false negative (FN) rate at lower overhead comparing with alternative approaches.

Microprobing is an invasive attack technique to intercept data from on-chip signals. As a countermeasure, we propose a new probing detector for an industrial sub-40 nm advanced process node. It is based on ring oscillators incorporating bus lines. The oscillation frequency caused by the capacity of bus lines is differentially measured to detect attached probes. This concept reduces calibration effort and required protected nonvolatile memory in comparison to state of the art. Furthermore, the protected bus line capacitance is increased up to four times. This work is the first analyzing the detector behavior considering cross coupling between the protected bus lines.

A persistent problem for modern Multi-Processors System-on-Chip (MPSoCs) is their vulnerability to code injection attacks. By tampering with the memory content, attackers are able to extract secrets from the MPSoC and to modify or deny the MPSoC's operation. This work proposes SEPUFSoC (Secure PUF-based SoC), a novel flexible, secure, and fast architecture able to be integrated into any MPSoC. SEPUFSoC prevents execution of unauthorized code as well as data manipulation by ensuring memory integrity and authentication. SEPUFSoC achieves: i) efficiency, through the integration of a fast and lightweight hash function for Message Authentication Code (MAC) generation and integrity verification of the memory lines at runtime; and ii) lightweight security, through the use of a Physical Unclonable Function (PUF) to securely generate and store the cryptographic keys that are used for the authentication of each application. We discuss the security and performance of SEPUFSoC for single core and multi-core systems. Results show that the SEPUFSoC is a secure, fast, and low overhead solution for MPSoCs.

The evaluation of the quality of physical unclonable functions (PUFs) is still under research. Most state-of-the-art metrics are found to measure only bias, while correlations, e.g., within the PUF response of a single device, remain unnoticed. In this paper, we introduce spatial autocorrelation analysis (SPACA), which is used in other fields of research, as a method to reveal correlations in the response of single-challenge PUFs. The presented statistics-Moran's I, Geary's c, and Join Count statistic-can be used to test the quality of an implementation using a set of sample devices as well as monitor ongoing production. Their results are also important for selecting an appropriate post-processing of the raw PUF response. Experiments on data sets from three different PUF implementations on field-programmable gate array and application-specific integrated circuit using SPACA show the capabilities of the introduced statistics. An efficient implementation of SPACA in MATLAB was developed to conduct the experiments. We discuss how SPACA can be used in practical testing and suggest to consider SPACA for a future test suite for PUFs.

Physical Unclonable Functions (PUFs) derive unique secrets from internal manufacturing variations in integrated circuits. This work shows that key generation with PUFs is a practical application of the generic information theoretic problem of secret key agreement with a compound source.

Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters. This paper presents a novel method for solving this type of discrete optimization problem. An iterative approach is presented, which is based on pseudo-gradients and a randomized calculation of search regions and steps. Experimental comparisons with simulated annealing and a continuous sizing approach with subsequent discretization clearly show the effectivity and efficiency of the presented method.