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EDBT 2026 Demo / reviewers in the wild / expert

Andrew Leaver

dblp:89/1674 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2000
0000-0001-5467-3145ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 64% Memory systems · 23% Integrated circuit design · 13%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA memory architecture
embedded memory blocks		 0.122000
Programmable memory blocks supporting content-addressable memory · FPGA 2000
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks · FPGA 1999
Memory systems
content-addressable memory		 0.012000
Programmable memory blocks supporting content-addressable memory · FPGA 2000

Methods — techniques the papers use, named apart from their topics

product term mode · 0.1CAM mode · 0.0dual port RAM · 0.0
YearPublicationVenuePosition
2000 Programmable memory blocks supporting content-addressable memory
abstract
The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as well as product term macrocells, ROM, and dual port RAM. In CAM mode each ESB can implement a 32 word CAM with 32 bits per word. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.
Frank Heile, Andrew Leaver, Kerry Veenstra
 FPGA2
1999 Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
abstract
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition to flexibly configurable ROM and dual port RAM. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.
Frank Heile, Andrew Leaver
 FPGA2