Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology the lack of information on the physical implementation during logic synthesis has caused mismatches between the final circuit characteristics (delay, power and area) and those predicted by logic synthesis. In this paper, we present a technique that tightly links the logic and physical domains-we combine logic and placement optimization in a single step. The combined algorithm is based on simulation annealing and hence, very amenable to new optimization goals or constraints. Two types of moves, directed towards global reduction in the cost function (linear congestion), are accepted by the simulated annealing algorithm: (1) logic optimization steps consisting of removing or replacing redundant wires in a circuit using functional flexibilities derived from SPFDs and (2) the placement optimization steps consisting of swapping a pair of blocks in the FPGA. Feedback from placement is very valuable in making an informed choice of a target wire during logic optimization moves. Experimental results demonstrate the efficacy of our approach over the placement independent approach.

This paper presents a new technique to perform power-oriented re-configuration of a system implemented using LUT FPGAs. The main features of our approach are: Accurate exploitation of degrees of freedom, concurrent optimization of multiple LUTs based on Boolean relations, and in-place re-programming without re-routing. Our tool optimizes the combinational component of the CLBs after layout, and does not require any re-wiring. Hence, delay and CLB usage are left unchanged, while power is minimized. As the algorithm operates locally on the various LUT clusters, it best performs on large examples as demonstrated by our experimental results: An average power reduction of 20.6% has been obtained on standard benchmarks.

We present an algorithm that restructures the state transition graph (STG) of a sequential circuit so as to reduce power dissipation.The STG is modified without changing the behavior of the circuit, by exploiting state equivalence.Bather than aiming primarily at reducing the number of states, our algorithm redirects transitions so that the new destination states are equivalent to the original ones, while the average activity of the circuit is decreased.The impact on area is also estimated to increase the accuracy of the power analysis.The STG and all other major data structures are stored as decision diagrams, and the algorithm does not enumerate explicitly the states or the transitions.(i.e., it is symbolic.)Therefore, it can deal with circuits that have millions of states.Once the STG has been restructured we apply symbolic factoring algorithms, based on Zero-suppressed BDDs, to convert the optimized graph into a multilevel circuit.We derive an efficient circuit from the BDDs of the STG by incorporating power constraints in the symbolic factoring algorithms.