This work addresses the use of reinforcement learning in the design of analog and mixed-signal (AMS) circuits. With recent advanced angstrom-technology-nodes adding new complexities, this highly manual process has grown increasingly challenging and less aligned with conventional design intuition. The presented approach modifies circuit topologies at the transistor-level to meet design requirements. We present, for the first time, a deep reinforcement learning (RL) framework capable of generating novel circuit topologies by using graph encodings for targeted specifications, starting from a minimal expert design and a user-specified testbench. To highlight the capabilities of the approach, we demonstrate the topological modification and expansion of incomplete sub-circuits to satisfy user-provided performance for three different types of circuits: 1) a ring oscillator, 2) a comparator, and 3) an operational transconductance amplifier. Our results demonstrate that our method is capable of generating previously unseen topologies that reach user-defined performance targets. In each design case, 100% of generated circuit netlists are correct by construction and over 90% of generated circuits demonstrate intended functionality and targeted performance when simulated with commercial tools.

In future networks, with the advent of massive machine type communications (mMTC), physical layer security is becoming a significant research area in the fifth generation (5G) and beyond 5G (B5G) communication systems. Device fingerprinting is a technology widely viewed to enhance the security of radio frequency (RF) based wireless systems. Meanwhile, visible light communication (VLC) is developing rapidly due to its remarkably high throughput in indoor situations and its security advantages for both privacy and health. In this paper, a VLC device fingerprint extraction and identification method are presented to improve the security of Visible Light Communication (VLC) in the 5G network. This method based on the fingerprint of Light Emitting Diodes (LEDs) has been investigated theoretically and verified experimentally. Moreover, a laboratory demonstration showed that the fingerprints of five identical white LEDs could be extracted and identified successfully. The best identification accuracy was up to 98.8%.

Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <; 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.

Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.

A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275μm2is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal.

This paper presents a hybrid TFET/CMOS SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like the IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while periphery is maintained in standard CMOS. The simulation extractions for power and speed are done including wiring and device parasitics extracted from 4Kb SRAM designed in 28nm FDSOI CMOS process. The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. The memory array leakage current is less than 1 fA/bit at sub-0.5V supply voltages, showing up-to 50x and 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells, respectively. Bitcell area is reduced by 3x in comparison to existing TFET designs. Evaluated static noise margin (SNM) is 100mV for supply voltages range from 0.2V to 0.6V. Minimum read and write access pulse is evaluated at 15ns at 0.45V supply voltage.

In this paper, an ultra-low-leakage TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad memory is proposed. DPSRAM cells are designed using TFETs to reduce the leakage power in the memory array as compared to CMOS. Peripheral circuits are designed using 28nm FDSOI technology to increase speed and to reduce area as compared to full TFET based memories. Performance and stability of the memory is analyzed for different supply voltages to support dynamic voltage frequency scaling (DVFS). Imbalanced single-ended sensing is proposed in the paper and different write-assist techniques are analyzed for the proposed TFET memory cell. In the analysis of TFET DPSRAM bitcell at 1V supply voltage the evaluated noise margins are 114mV and 185 mV for read and write, respectively, with a 5 orders of magnitude reduction in leakage as compared to a similar CMOS bitcell. Results of performance evaluation of the designed 32Kb TFET/CMOS DPSRAM show a gain of up to 79.2% in write speed using write assist at sub-1V supply voltages and less than 1 ns read/write cycle time for more than 1V supply voltages.

This paper presents a predictive analysis of the high-density SRAM cell scaling from the stability and low power perspective. Based on a subthreshold SRAM analytical model [5] and a SRAM area-scaling model the Data Retention Voltage (DRV) defined as the lowest VDDthat can be applied during standby without losing data, as well as the minimum supply voltage for reliable read and write (VMIN), are investigated. The analysis is performed for several future technology nodes down to the 18 nm node. It takes into account the impact of MOS key parameters: threshold voltage (VT), subthreshold slope, DIBL, body factor and Pelgrom's Coefficient AVT. It is demonstrated, that due to process variations, the use of bulk CMOS for sub-28 nm becomes very challenging and severely limits area and supply scaling. Thin-film technology such as Ultra-Thin Body and BOX (UTBB) FDSOI however, should allow stable and power- and area-efficient SRAM design scaling below the 22 nm node with DRV lower than 0.4 V.

This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability constraints in all operating modes. An accurate analytical SRAM subthreshold model is developed for characterizing the cell behavior and optimizing its performance. The proposed design approach is demonstrated for an SRAM implemented in a 32nm CMOS UTBB-FDSOI technology. Stable operation in both read and write is obtained for the optimized cell at VDD=0.4V. Moreover, in the optimization process the standby and active power were reduced up to 10x and 3x, respectively.

This paper describes the applicability of Tunnel FETs to commercial embedded Static Random-Access Memories (SRAM). Numerical device simulations were used first to optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its stability is analyzed. Our novel 8T TFET SRAM cell operates at VDD=1V. The Read and Write Static Noise Margins are evaluated at 120mV and 200mV, with the operation speed of 300MHz and 1GHz in read and write respectively. The cell leakage is less than 10fA at VDD=1V. Our results show that TFETs are excellent candidates for embedded SRAMs due to their Ultra-Low Standby Power (LSTP).

A low-cost and high-manufacturability Multi-VTUltra-Thin BOX and Body (UT2B) FDSOI technology is proposed for high-performance and low-leakage digital circuits. This concept allows setting up low, standard and high threshold voltage (VT) devices without degrading the good channel electrostatic control and the low VTdispersion of the FDSOI technology. Device electrical characteristics, process flow and physical design are described and the performance of digital circuits is evaluated.

This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to Vthand L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.

This paper presents a comparative study of sub-32 nm CMOS 6T and 4T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Both independent- and connected-gate operation is analyzed by modulating the drain current with both front and back gate voltages. An improved 4T driver-less (DL) SRAM cell is proposed which takes advantage of the back gate to improve stability in read and retention mode by applying feedback between access transistor and storage node. The results of statistical characterization of read-, retention- and write margins, power and access time are presented for all cells in the presence of process variability.

A design methodology for analog circuit blocks is proposed which combines circuit knowledge and high-level general-purpose math packages with CAD simulation tools. The proposed flow of the design of a complex analog or mixed-signal system starts with a conceptual phase setting performance goals for each block, Followed by an exploration phase based on analytical descriptions resulting in the selection of a performance point in the design space and an implementation phase resulting in the sizing of the transistors in each block. The final phase of the electrical design is verification, optimization and design centering in SPICE using foundry-provided process data. It is shown that numerical optimization available in some SPICE offerings such as Eldo deliver a design that not only meets specifications but delivers optimal performance for a selected objective within given constraints

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pseudosaturation regions of MOS transistors operated below V/sub T/. It can be applied for predicting bulk- or partially depleted (PD) SOI CMOS circuit operation. Analytical expressions derived for the logic switching threshold and delay are applied to predict the performance of CMOS-SOI inverters.

A transformer model which consists of a nonlinear core with hysteresis and multiple windings is described as implemented in DSPICE. In contrast to previous implementations, the nonlinear behavior of the new model is described by continuous piecewise-hyperbolic functions characterized by three parameters. These parameters are the same as parameters previously published in the literature. A loop-traversing algorithm has been implemented which avoids discontinuities and eliminates both nonconvergence problems and the occurrence of erroneous voltage spikes during time-domain simulation. In the large-signal time-domain analysis the frequency-dependent eddy current losses in the core and wire losses are modeled. Additional effects, such as wire skin effect and temperature dependence, are also included. In the small-signal AC analysis the transformer is modeled as frequency-dependent lossy mutual inductors. For both analyses, the air gap and the elated fringe field effect are modeled by extending the magnetic path length of the core appropriately.>

A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.