Cycle-level simulators such as gem5 are widely used in microarchitecture design, but they are prohibitively slow for large-scale design space explorations.We present Concorde, a new methodology for learning fast and accurate performance models of microarchitectures.Unlike existing simulators and learning approaches that emulate each instruction, Concorde predicts the behavior of a program based on compact performance distributions that capture the impact of different microarchitectural components.It derives these performance distributions using simple analytical models that estimate bounds on performance induced by each microarchitectural component, providing a simple yet rich representation of a program's performance characteristics across a large space of microarchitectural parameters.Experiments show that Concorde is more than five orders of magnitude faster than a reference cycle-level simulator, with about 2% average Cycles-Per-Instruction (CPI) prediction error across a range of SPEC, open-source, and proprietary benchmarks.This enables rapid design-space exploration and performance sensitivity analyses that are currently infeasible, e.g., in about an hour, we conducted a first-of-its-kind fine-grained performance attribution to different microarchitectural components across a diverse set of programs, requiring nearly 150 million CPI evaluations.

Graph Neural Networks (GNNs) have greatly advanced the semi-supervised node classification task on graphs. The majority of existing GNNs are trained in an end-to-end manner that can be viewed as tackling a bi-level optimization problem. This process is often inefficient in computation and memory usage. In this work, we propose a new optimization framework for semi-supervised learning on graphs from a multi-view learning perspective. The proposed framework can be conveniently solved by the alternating optimization algorithms, resulting in significantly improved efficiency. Extensive experiments demonstrate that the proposed method can achieve comparable or better performance with state-of-the-art baselines while it has significantly better computation and memory efficiency.

Ahstract— With the rapid development of vehicular applications and mobile devices, demands for resources to process time-critical and computation-intensive tasks are increasingly prominent. In this paper, we propose a two-layer Vehicular Fog Computing (VFC) architecture, including the client layer and the fog layer. Vehicles may generate tasks as clients, which are further assigned to the nodes in the fog layer for processing. The fog layer aggregates available resources of vehicles and infrastructures by exploiting their communication, computation and storage capabilities. Each task requires certain amount of resources for processing at the fog nodes. We formulate a distributed task allocation (DTA) problem, which takes deadline, vehicle mobility and fog capacity into consideration, and aims at maximizing the overall resource utilization of system, via the cooperation of vehicles and fog nodes. We linearize DTA into a 0–1 integer linear programming (ILP) problem to obtain the optimal solution. Further, we design a heuristic algorithm to obtain near-optimal performance with low computational overhead, which decomposes DTA into two subprocess and schedules tasks in each fog node independently. Finally, we build the simulation model and conduct a series of experiments based on real-world vehicle trajectories, which demonstrate the effectiveness and scalability of the proposed algorithm.

With recent development of wireless communication, sensing and computing technologies, Internet of Vehicles (IoV) has attracted great attention in both academia and industry. Services with low communication latency and high reliability are necessary to enable safety-critical applications in IoV. Nevertheless, it is challenging to satisfy the service requirement due to unique characteristics of IoV, including limited wireless communication bandwidth, high vehicle mobility, massive data transmission, and overwhelming computation overhead. In view of this, we propose a novel vehicular fog computing (VFC) architecture to explore the synergistic effect of the cloud, the static fog and the mobile fog by defining corresponding service modes. On this basis, we further formulate a task offloading model, which quantitatively analyzes the characteristics of the three service modes and enables task offloading based on particular service requirements. Finally, we implement a traffic abnormity detection and warning system based on the proposed architecture as a case study. The hardware-in-the-loop performance evaluation not only demonstrates the effectiveness of the proposed architecture, but also enlightens future research directions on developing adaptive task offloading for dynamic IoV applications.

The marketplace for general-purpose microprocessors offers hundreds of functionally similar models, differing by traits like frequency, core count, cache size, memory bandwidth, and power consumption. Their performance depends not only on microarchitecture, but also on the nature of the workloads being executed. Given a set of intended workloads, the consumer needs both performance and price information to make rational buying decisions. Many benchmark suites have been developed to measure processor performance, and their results for large collections of CPUs are often publicly available. However, repositories of benchmark results are not always helpful when consumers need performance data for new processors or new workloads . Moreover, the aggregate scores for benchmark suites designed to cover a broad spectrum of workload types can be misleading. To address these problems, we have developed a deep neural network (DNN) model, and we have used it to learn the relationship between the specifications of Intel CPUs and their performance on the SPEC CPU2006 and Geekbench 3 benchmark suites. We show that we can generate useful predictions for new processors and new workloads . We also cross-predict the two benchmark suites and compare their performance scores. The results quantify the self-similarity of these suites for the first time in the literature. This work should discourage consumers from basing purchasing decisions exclusively on Geekbench 3, and it should encourage academics to evaluate research using more diverse workloads than the SPEC CPU suites alone.

We propose and evaluate two complementary techniques to protect and virtualize a tightly-coupled network interface in a multicomputer. The techniques allow efficient, direct application access to network hardware in a multiprogrammed environment while gaining most of the benefits of a memory-based network interface. First, two-case delivery allows an application to receive a message directly from the network hardware in ordinary circumstances, but provides buffering transparently when required for protection. Second, virtual buffering stores messages in virtual memory on demand, providing the convenience of effectively unlimited buffer capacity while keeping actual physical memory consumption low. The evaluation is based on workloads of real and synthetic applications running on a simulator and partly on emulated hardware. The results show that the direct path is also the common path, justifying the use of software buffering. Further results show that physical buffering requirements remain low in our applications despite the use of unacknowledged messages and despite adverse scheduling conditions.

The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to express each algorithm's dependencies and to support automatic synthesis, partitioning, and mapping to a reconfigurable computer. Within this framework, each benchmark is portably designed in both C and Behavioral Verilog and scalably parameterized to consume a range of hardware resource capacities. To establish initial benchmark ratings, we have targeted a commercial logic emulation system based on virtual wires technology to automatically generate designs up to millions of gates (14 to 379 FPGAs). Because the virtual wires techniques abstract away machine-level details like FPGA capacity and interconnect, our hardware target for this system is an abstract reconfigurable logic fabric with memory-mapped host I/O. We report initial speeds in the range of 2X to 1800X faster than a 2.82 SPECint95 SparcStation 20 and encourage others in the field to run these benchmarks on other systems to provide a standard comparison.