Hideyuki Kabuo

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2ranked-venue papers

1as first author

0since 2021 · last 1994

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design › digital circuit design arithmetic circuit design	1	1994	Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation · IEEE Trans. Computers 1994
Integrated circuit design › digital arithmetic circuits › division and square root floating-point division and square root	1	1994	Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation · IEEE Trans. Computers 1994
Integrated circuit design › digital arithmetic circuits › floating-point unit design rounding	1	1994	Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation · IEEE Trans. Computers 1994
Integrated circuit design › redundant number representation redundant binary representation	1	1994	Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

newton-raphson method · 0.0

Year	Publication	Venue	Position
1994	Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation abstract Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly.> Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu	IEEE Trans. Computers	1
1988	A programmable fuzzifier integrated circuit--synthesis, design, and fabrication Takeshi Yamakawa, Hideyuki Kabuo	Inf. Sci.	2