Based on a CGS (conjugate gradient squared) iteration with a partitioned natural ordering, a novel massively parallel algorithm for three-dimensional device simulation is presented. This algorithm requires constant time per matrix iteration independent of the number of grid nodes, and has convergence properties comparable to those of good algorithms currently used on sequential computers. This algorithm has been implemented on the Connection Machine and achieves supercomputer performance for large numbers of grid nodes. Results are presented for a wide variety of devices and mesh sizes.>

The question of whether or not the convenient stored-charge (SC) method is appropriate to calculate small-signal characteristics of bipolar devices is considered. A general definition of the total SC capacitance of a semiconductor device, and an expression for the difference with the AC capacitance are presented. The SC method is found to yield correct capacitance for practical p-n junction diodes at moderate and high forward bias. The discrepancy is attributed to the diffusive delay of minorities and is seen to be enhanced by ohmic fields. Nevertheless, the SC method accurately predicts the common-emitter input capacitance of a bipolar transistor with a high current gain and a low base resistance, in spite of its forward-biased emitter-base junction. The various methods proposed in the literature to derive the cutoff frequency from AC small-signal parameters are found to disagree with the SC method as well as with each other if the current gain is lower than about five. Especially at low current gain, Gummel's cutoff frequency is found to be preferable, both for simulations and for measurements.>

Intrinsic MOSFET capacitances are calculated using the three-dimensional ac device simulator CADDETH, and distributions of the internal ac currents are studied. The simulations clearly show the influence of velocity saturation. Finally short-channel effects on the intrinsic MOSFET capacitances are analyzed.

This paper describes a statistical model for circuit simulation that predicts variations in circuit behavior. This model includes parameter matching considerations critical to analog integrated circuits (IC's). The model is based on experimental data gathered from standard production bipolar-analog integrated chips. By using multivariate statistical techniques, the model is constructed having the two kinds of sub-models. One sub-model uses the eigenvalues and vectors of the correlation matrix, and then generates the correlation between devices on a chip. the other uses linear regression equations and generates the correlation within a device. The model has been implemented into a circuit simulator and statistical circuit simulations are performed. Measured device parameter variations in analog IC's are well reproduced within the practical execution time by the model. Simulation examples for analog IC's are demonstrated to illustrate the effectiveness of the model.

A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can be obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFET's can be readily simulated with good convergence and good agreement with experimental results.