The Internet-of-Things (IoT) devices feature a broad range of power, memory, and performance requirements. Ultralow-power, low-performance controllers are at one end of the spectrum, while high-performance, power-intensive systems-on-chip (SoCs) are at the other. Heterogeneous and specialized multiprocessor SoC (MPSoC) architectures have emerged as the most effective paradigm for delivering high performance and energy efficiency across a wide range of application workloads. This work introducesHeadsail, an MPSoC application-specific integrated circuit (ASIC) designed by SoC Hub at Tampere University, Finland.Headsailfeatures a 512-KiB primary data buffer, 128 KiB of shared on-chip SRAM, seven CPU cores (including four CVA6 64-bit RISC-V processors), a low power-DDR2 (LP-DDR2) memory controller, two unique chip-to-chip (C2C) interfaces, and shared peripherals.Headsailhas been successfully implemented using a TSMC 22-nm low-power CMOS technology. Testing results show that the samples can support a maximum operating frequency of 1 GHz and achieve a peak performance of 1100 giga operations per second (GOPS), with an implementation area of 25 mm2and a power-consumption range of 64 mW–1.5 W.

Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.

Context switching is both a highly utilized and highly repetitive routine in interrupt-driven systems, such as safety-critical control systems. Conventional context switching routines are sequential and dependent on data memory access, which may be detrimental to time-predictability. This publication explores the use of stacked register files for efficient and predictable context switching. Two complementary microarchitectures are characterized: combinationally addressed register windowing, and a novel parallel context stack (PCS). Both implementations enable minimal latency and inherent predictability in context switching. To efficiently utilize the benefit of stacked register files while limiting hardware costs, the heterogeneous interrupt (HETI) architecture is proposed. HETI integrates a small stacked register file for accelerating a dynamically selected subset of high-priority interrupts. Automatic firmware generation is contributed to enable seamless utilization of the HETI architecture. A total of four HETI configurations on an open-source RISC-V microcontroller are evaluated against the baseline platform and an implementation of Cortex-M style hardware-assisted stacking. Implementations on a TSMC 22nm technology demonstrate low area overhead for small HETI configurations and favorable frequency characteristics against the hardware-assisted stacking implementation. A representative layout of the full system with a HETI-4 instance is presented with a gate count overhead of 1.2% and no frequency detriment in relation to the baseline design. The functional performance evaluated in a synthetic case study demonstrates how the HETI design can reduce retired instruction count by up to 26% and allow for 21% more sleep in comparison to the software baseline and Cortex-M style solution, promising significant improvements to real-time response and energy efficiency.

The recent trend towards open architectures and open source hardware enables agile development of domain specific architectures. In this paper, we explore and propose the design and implementation of AnTiQ, a hardware-accelerated priority queue tailored to the needs of timer queue implementations and other cases where removal of arbitrary elements, a feature we found lacking in related work, is desirable. The key novelty of AnTiQ is the arbitrary remove or DROP operation, which along with PUSH, POP and PEEK is performed in constant time. The design was conceived by reviewing existing implementations of hardware priority queues and analysing the fundamental characteristics of three queue architectures: the shift register queue, the systolic array queue and the binary heap queue. The systolic array architecture was chosen for our design due to its pipelined structure and ability to provide constant time responses to queue operations regardless of the queue depth. The architecture and implementation of our RTL prototype is presented and relevant behavioural corner cases in the design are identified. The implementation of our design achieved a clock frequency of 350 MHz on a Xilinx VCU 118 FPGA. The scalability of the design is evaluated through FPGA synthesis for 32, 64, 128 and 256 depth configurations and compared to the related work. We elaborate on directions for further development and future work towards monotonic timer implementations for the RTIC framework, a domain specific Rust language extension for concurrent programming targeting bare metal microcontrollers.

This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap processor and customized to meet our requirement for guaranteed chip wake-up. We outline the characteristic challenges of implementing a large program into a read-only memory (ROM) used for booting and propose generally applica-ble workflows to verify the boot process for application specific integrated circuit (ASIC) synthesis. We implemented four distinct boot modes. Two modes that load a software bootloader autonomously from an SD card are implemented for a secure digital input output (SDIO) interface and for a serial peripheral interface (SPI), respectively. Another SDIO based mode allows for direct program execution from external memory, while the last mode is based on usage of a RISC- V debug module. The boot process was verified with instruction set simulation, register transfer level simulation, gate-level simulation and field-programmable gate array prototyping. We received the fabricated ASIC samples and were able to successfully boot the chip via all boot modes on our custom circuit board.