Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moore's Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,… beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, A&M/S, MEMS,… Choosing the right road is critical to lead your project and your company to success, but making the right decision is increasingly difficult, as it encompasses complex technical and economic considerations. However, unlike the mythological traveler, you won't run into the sphinxes but, rather, into some of our industry best experts; unlike the sphinxes, they will strive to provide you with honest advice about the “road conditions”, and you are allowed to ask multiple questions to them to figure out which road is the best for you.

UTBB FD-SOI technology has become mainstream within STMicroelectronics, with the objective to serve a wide spectrum of mobile multimedia products. This breakthrough technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. The symbiosis between process and design is key in this achievement enabling to provide already at 28nm node a real differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market.

The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and "How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain "Are we there yet?" "Is it now or the future?"

Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details", and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards". We are looking forward to an exciting discussion that will challenge our esteemed panelists

Designing in 45nm allows another doubling in transistor density vs 65nm, both for logic gates and for SRAM cells. However, Lithography implications are such that Design rules have to be augmented with recommended rules and regular design, and verified with full Lithography and CMP simulation. Low-power techniques have to be even more elaborate than in 65nm, to compensate for less natural voltage swing in logic and SRAMs, and more gate leakage. Finally, reliability and ESD models have to be taken into account by design and phenomena such as Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are part of library and chip design verification suites. It is only with a holistic approach encompassing process, device modeling, reliability, litho, memory designers, IO designers, power switch experts, that the full capabilities of the 45nm node will be unleashed.

Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists from the world's top technology companies are striving to improve their chances of success. Will leakage constraints force power-sensitive applications to stay with older technologies, or will there be a bifurcation to a new process technology? Will ballooning capital equipment expenses delay new capacity or price out design rules for mainstream applications? Will silicon-on-insulator and new device structures like FinFETs force rethinking of design, modeling and simulation methodologies? And which EDA technologies, delivered when, will be critical for victory? These senior technologists, from some of the biggest companies in the high tech industry, will discuss and debate how they think the overall industry will successfully transition to the nanometer age. Specific examples from the technologists' broad exposure to industry trends and competitors will help illustrate their forecasts and predictions.

No abstract available.

In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on design automation requirements, from the perspective of a broad range SoC supplier.We present our vision of some of the key changes that will emerge in the next five years. This vision is characterized by two major paradigm changes. The first is that SoC design will become divided into four mostly non-overlapping distinct abstraction levels. Very different competences and design automation tools will be needed at each level.The second paradigm change is the emergence of domain-specific S/W programmable SoC platforms consisting of large, heterogeneous sets of embedded processors. These will be complemented by embedded reconfigurable hardware and networks-on-chip. A key enabler for the effective us of these flexible SoC platforms, is a high-level parallel programming model supporting automatic specification-to-platform mapping.

Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing “food chain” need to work together to drive greater efficiencies?