The floating point performance of superscalar SPARC processors is evaluated based on empirical data horn 12 benchmarks.This evaluation is done in the context of two software instruction scheduling optimization, loop unrolling and software pipelining, and for three machine models we term, 1-scalar, 2-scalar and 4-scalar.We also consider the effect of the memory system on the performance improvements.Superscalar hardware alone exhibit little performance improvement without software optimization.Of the two scheduling methods we study, software pipelining more effectively takes advantage of increased hardware parallelism, and achieves near optimal speedup on the 4-scalar machine model.The performance of loop unrolling is restricted by the limited number of floating point registers in the SPARC architecture.The best performance level is obtained by applying both optimization techniques.A superscalar SPARC processor can provide improved tloating point performance but with significant software and hardware development costs.

The problem studied is similar to the problems found in multiprocessor operating systems. The lockout problem in multiprocessor operating systems is a direct result of multiple processors attempting to process common data structures asynchronously. There are numerous such shared data structures. The models developed are applicable to the study of contention for software and hardware resources in multiprocessor operating systems. The authors introduce an approximate analytical model to evaluate the performance of asynchronous processes found in asynchronous algorithms, including the combined effects of software lockout on critical sections and on job queues, and of shared-memory access conflicts. Because of the strong similarities between the two effects, the same model can be used for both, leading to a uniform and elegant formulation. The models are combined to find the run-time efficiency of asynchronous iterations.>

In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access latency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. Write buffers are often included in a pipelined machine to avoid processor waiting on writes. In a shared memory multiprocessor, there are more advantages in buffering memory requests, since each memory access has to traverse the memory- processor interconnection and has to compete with memory requests issued by different processors. Buffering, however, can cause logical problems in multiprocessors. These problems are aggravated if each processor has a private memory in which shared writable data may be present, such as in a cache-based system or in a system with a distributed global memory. In this paper, we analyze the benefits and problems associated with the buffering of memory requests in shared memory multiprocessors. We show that the logical problem of buffering is directly related to the problem of synchronization. A simple model is presented to evaluate the performance improvement resulting from buffering.

A possible design alternative for improving the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers by reducing the effective memory access time, and affect the delays caused by memory conflicts. In this paper, we study the effectiveness of caches in a multiprocessor system. The shared memory is pipelined and interleaved to improve the block transfer rate, and it assumes a two-dimensional organization, previously studied under random and word access. An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches.

In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches. In this paper, we present an indepth analysis of the effect of cache coherency in multiprocessors. A novel analytical model for the program behavior of a multitasked system is introduced. The model includes the behavior of each process and the interactions between processes with regard to the sharing of data blocks. An approximation is developed to derive the main effects of the cache coherency contributing to degradations in system performance.

The PUMPS architecture consists of P task processing units (TPU) which share a pool of special peripheral processors, VLSI functional units, and a common two-dimensional shared memory (SM) via a block transfer oriented interconnection network. A shared cache is provided between the TPU's and SM for efficient MIMD interprocessor communication. The SM is also connected via a backend database management network (BDMN) with distributed control to the file memories, which are disk-based database storage devices.

In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches. In this paper, we present an in-depth analysis of the effects of cache coherency in multiprocessors. A novel analytical model for the program behavior of a multitasked system is introduced. The model includes the behavior of each process and the interactions between processes with regard to the sharing of data blocks. An approximation is developed to derive the main effects of the cache coherency contributing to degradations in system performance.

A general methodology for studying the degree of matching between an architecture and an algorithm is introduced and applied to the case of synchronized iterative algorithms in MIMD machines.

A possible design alternative to improve the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers, reducing the memory access time, and affect the delays caused by memory conflicts. In this paper, we study the performance of a multiprocessor system with caches. The shared memory is pipelined and interleaved to improve the block transfer rate, and assumes an L-M organization, previously studied under random word access. An approximate model is developed to estimate the processor utilization and the speedup improvement provided by the caches. These two parameters are essential to a cost-effective design. An example of a design is treated to illustrate the usefulness of this investigation.

A simulation model is developed and used to study the effect of buffering of memory requests on the performance of multiprocessor systems.

The performance of various memory configurations for parallel-pipelined computer which execute multiple instruction streams on multiple data streams is investigated.

An organization of interleaved multimodule semiconductor memories is studied to facilitate accessing of memory words by a parallel-pipelined processor. All modules are assumed to be identical and to have address cycle (address hold time) and memory cycle of a and c segment time units, respectively. A total of N(=2n) memory modules are arranged such that there are l(=2b) lines for addresses and m(=2n-b) memory modules per line. For a parallel-pipelined processor of order (s,p) which consists of P parallel processors each of which has s degrees of multiprogramming, there can be up to s · p memory requests in each instruction cycle. Memory request collisions are bound to occur in such a system. Performance is evaluated as a function of the memory configuration. Results show that for reasonably large values of N, high performance can be obtained even in the nonbuffered case when l is a · p or more. Buffering has maximum effect on performance when l is near a · p. When l must be grater than a · p for adequate performance in the nonbuffered case, buffering can be used to reduce l while maintaining performance.