A 5-DC-parameter model presented in [1] , the ACM2.0 [2] , was carried out with the description language Verilog- A [3] , to simulate circuits using open-source EDA tools ngspice/Xschem with the help of the conversion tool OpenVAF [4] .

In this article we focus on the understanding of the MOSFET behavior allowed by the ACM2.0 model proposed last year. We discuss the concept of inversion level and its relationship with the carrier density taking velocity saturation into account. The extraction of the five DC parameters of the model based on circuit simulations is briefly developed, accounting for second-order effects. Finally, simple expressions for the drain current, the gate transconductance as well as the third-order derivative of the current with respect to the gate voltage, including the velocity saturation phenomenon, are provided.

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180$\text{G}\Omega $and 700$\text{G}\Omega $were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

This brief describes a compact test chip in a 130-nm CMOS technology, aimed at characterizing both the short- and long-channel transistors and the series association of halo-implanted transistors. The chip contains a set of low-threshold-voltage (LVT) nMOS/pMOS transistors with several channel lengths and transistors associated in series. Parameters, such as threshold voltage, specific current, and intrinsic voltage gain, were determined through simulation and measurements of 20 chips. The results reported herein provide integrated circuit designers with guidelines for choosing either long-channel lengths or series association of transistors to comply with the requirements of their design.

This work presents a self-biased MOSFET threshold voltage VT0monitor. The threshold condition is defined based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit consists in balancing two self-cascode cells operating at different inversion levels, where one of the transistors that compose these cells is biased at the threshold condition. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. We propose a process independent design methodology, evaluating different trade-offs of accuracy, area and power consumption. Schematic simulation results, including Monte Carlo variability analysis, support the VT0monitoring behavior of the circuit with good accuracy on a 180 nm process.

This paper presents the temperature performance of two self-biased current sources. We have employed a simple topology to design 4 nA and 900 pA current references implemented in both 0.35 mum and 0.18 mum technologies, respectively. Experimental results showed that the current source implemented in 0.35 mum technology can operate at a supply voltage as low as IV and at 650 mV in 0.18 mum CMOS technology. The temperature performance of the current source is analyzed in this paper. The association of a very simple topology, an efficient design procedure, low voltage cascode transistor and low output conductance trapezoidal transistors has resulted in small area, ultra low power consumption and a line regulation better than 0.2%/V of supply voltage.

This paper presents a new approach for accurate M-2M MOSFET digital-to-analog converter (DAC) design. It describes a complete design methodology, where DAC inaccuracy is related to transistor geometry and bias through a powerful physics-based MOSFET mismatch model, very useful for hand design. Short-channel effects are also taken into account. Two versions of the converter were implemented in a 0.35 ¼m 3.3V CMOS technology, and corroborate the theoretical development with statistical experimental results.

This paper presents a simple model of the Early voltage for the MOS transistor operating in weak and moderate inversion. The model is based on a decomposition of the transistor channel into a region where the gradual-channel approximation holds and a region that is modeled as a reverse-biased juntion. Measurements of the characteristics of both nand p-channel transistors with different channel lengths in a 0.35 μm technology demonstrate the feasibility of the proposed model.

In this paper, we propose a CMOS fully balanced sample-hold amplifier. The proposed circuit is based on the technique described by Goncalves et al. (1996), which is appropriate for low voltage operation. The programmability of the sample-hold circuit is achieved via the MOSFET Only Current Divider (MOCD). We present a new method for sign-bit realization using the two output currents of the MOCD. The programmable S/H circuit is designed to be fabricated in a 0.8 /spl mu/m CMOS technology with /spl plusmn/0.75 V power supply.

This paper presents a design procedure for amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. It is shown that there is an optimum bias in moderate inversion for which the attainable DC gain is maximum. The design and measurements of a common-source amplifier illustrate the appropriateness of the proposed methodology.

In this paper, we propose a very simple bias circuit that allows for maximum output voltage swing of MOSFET cascode stages. The proposal is valid for any current density and is technology-independent. Starting from the saturation voltage and from the current density of the cascode stage, we determine the aspect ratio of the transistors in the bias circuit in order to maximize the output voltage swing. Experimental results validate the strategy for designing the bias network.

This paper presents an explicit analytical model of the MOS transistor valid in all regions of operation weak, moderate and strong inversion. The proposed model, physically derived, uses the inversion charge density as the key variable and is very simple to be incorporated in CAD programs. Moreover, our model contains only the classical parameters of the MOSFET theory. The inclusion of our model in SABER has led to simulation results which agree very closely with experiments.

This paper presents a simple approach to design composite FET's with low output conductance. These composite transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a much higher cutoff frequency.>