Thickness range, i.e. the difference between the highest point and the lowest point of the chip surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm that seeks to minimize the thickness range of the chip surface during the copper damascene process. The proposed solution considers the physical mechanisms in the damascene process, namely ECP (which is the process used to deposit Cu in the trenches) and CMP (which is the process used to polish Cu after ECP), that affect thickness range. Key predictors for the final thickness range, which is the thickness range after ECP and CMP, that can be computed efficiently are identified and used to drive the metal filling process. To the best of our knowledge, this is the first metal filling algorithm that uses an ECP model among other things to guide metal filling. Experimental results are very promising and indicate that the proposed method can significantly reduce the thickness range after metal filling. This is in sharp contrast with the density-driven approaches which often increase the thickness range after metal filling, thereby potentially adversely impacting yield. In addition, the proposed method inserts significantly smaller amount of fill when compared to the density-driven approaches. This is desirable as it limits the impact of metal filling on timing.

In deep submicron feature sizes continue to shrink aggressively beyond the natural capabilities of the 193 nm lithography used to produce those features thanks to all the innovations in the field of resolution enhancement techniques (RET). With reduced feature sizes and tighter pitches die level variations become an increasingly dominant factor in determining manufacturing yield. Thus a prediction of design-specific features that impact intra-die variability and correspondingly its yield is extremely valuable as it allows for altering such features in a manner that reduces intra-die variability and improves yield. In this paper, a manufacturing yield model which takes into account both physical layout features and manufacturing fluctuations is proposed. The intra-die systematic variations are evaluated using a physics-based model as a function of a design's physical layout. The random variations and their across-die spatial correlations are obtained from data harvested from manufactured test structures. An efficient algorithm is proposed to reduce the order of the numerical integration in the yield model. The model can be used to (i) predict manufacturing yields at the design stage and (ii) enhance the layout of a design for higher manufacturing yield.

In this paper, a layout dependent full-chip electroplating (ECP) topography model is developed based on the additive nature of the physics of the EP process. Two layout attributes: layout density, and feature perimeter sum are used to compute the post-ECP topography. Under a unified mechanism, two output variables representing the final topography: the array height and the step height are modeled simultaneously. Using the proposed model long-range effects of the ECP process can be incorporated easily as well. The simulation results of our model were verified with test structure experimental data published in the literature and are presented in this paper. The results show that the errors are less than 5%. This model is not limited to the regular test structures; it can also be used for any practical design. The results of such partial application are shown here as well. Our proposed ECP model can be used to model systematic variations caused by an ECP process or by a chemical mechanical planarization (CMP) process. The potential applications of this model include: layout design evaluation for catastrophic failure prevention; yield aware design (design for manufacturability), and variation- aware timing analysis.