In high-speed network processors, data queueing has to allow real-time memory (de)allocation, buffering, retrieving, and forwarding of incoming data packets. Its implementation must be highly optimized to combine high speed, low power, large data storage, and high memory bandwidth. In this paper, such data queueing is used as case study to demonstrate the effectiveness of a new system-level exploration method for optimizing the memory performance in dynamic memory management. Assuming that a multi-bank memory architecture is used for data storage, the method trades off bank conflicts against memory accesses during real-time memory (de)allocation. It has been applied to the data queueing module of the PRO3 system [8]. Compared with the conventional memory management technique for embedded systems, our exploration method can save up to 90% of the bank conflicts, which allows to improve worst-case memory performance of data queueing operations by 50% too.

We present a new exploration and optimization method at the system level to select customized implementations for dynamic data sets, as encountered in telecom network, database, and multimedia applications. Our method fits in the context of embedded system synthesis for such applications, and enables to further raise the abstraction level of the initial specification, where dynamic data sets can be specified without low-level details. Our method is suited for hardware and software implementations. In this paper, it mainly aims at minimizing the average memory power, although it can also be driven by other cost functions such as memory size and performance. Compared with existing methods, for large dynamic data sets, it can save up to 90% of the average memory power, while still saving up to 80% of the average memory size.

Presents a new methodology for dynamic memory management of embedded telecom network systems. This methodology enables the designer to further raise the abstraction level of the initial system specification and to achieve optimized embedded system designs. This methodology is well suited for systems characterized by a set of concurrent and dynamic processes, very high-bit-rate data streams, and intensive data transfer and storage, as encountered in telecom network applications. Up to now, it has been successfully applied to four telecom network systems. This methodology can be easily integrated into any C++-based system synthesis approach that bridges the gap between a concurrent process-level system specification and an optimized (for area, performance, or power) embedded implementation of communicating hardware/software processors. This is in contrast to current system design practice, where VHDL/C is derived without room for exploration, refinement, and verification, leading to expensive late design iterations. In this paper, the main focus lies on the system-level specification model and the dynamic memory management applied to two real-life telecom network systems.