In this study, a novel multi‐layer fused convolution neural network (MLF‐CNN) is proposed for detecting pedestrians under adverse illumination conditions. Currently, most existing pedestrian detectors are very likely to be stuck under adverse illumination circumstances such as shadows, overexposure, or nighttime. To detect pedestrians under such conditions, the authors apply deep learning for effective fusion of the visible and thermal information in multispectral images. The MLF‐CNN consists of a proposal generation stage and a detection stage. In the first stage, they design an MLF region proposal network and propose to use summation fusion method for integration of the two convolutional layers. This combination can detect pedestrians in different scales, even in adverse illumination. Furthermore, instead of extracting features from a single layer, they extract features from three feature maps and match the scale using the fused ROI pooling layers. This new multiple‐layer fusion technique can significantly reduce the detection miss rate. Extensive evaluations of several challenging datasets well demonstrate that their approach achieves state‐of‐the‐art performance. For example, their method performs 28.62% better than the baseline method and 11.35% better than the well‐known faster R‐CNN halfway fusion method in detection accuracy on KAIST multispectral pedestrian dataset.

In this study, the authors present a new efficient method based on discriminative patches (d‐patches) for holistic traffic sign detection with occlusion handling. Traffic sign detection is an important part in autonomous driving, but usually hampered by the occlusions encountered on roads. They propose a method which basically upgrades d‐patches by integrating vocabulary learning features. Consequently, d‐patches are more discriminatively trained for robust occlusion handling. In addition, a holistic classifier is trained on d‐patches, which identify those regions where occlusion exists. This results in higher confidence‐score for the regions which contain traffic signs and lower confidence‐score for the regions containing occlusions. Furthermore, they also propose a new coarser‐to‐fine (CTF) approach to speed up the traffic sign detection process. CTF minimises the use of traditional sliding window for object detection. It relies on colour variance to search the regions with high probability of traffic sign presence. Sliding window is used only on the selected high probability regions. The proposed method achieves 100% detection results on German Traffic Sign Detection Benchmark and performs 2.2% better than the previous state‐of‐the‐art methods on Korean Traffic Sign Detection dataset, under partially occluded settings. By using CTF approach, five times speedup with a marginal loss in accuracy can be achieved.

In advanced driver assistance systems, accurate detection of traffic signs plays an important role in extracting information about the road ahead. However, traffic signs are persistently occluded by vehicles, trees, and other structures on road. Performance of a detector decreases drastically when occlusions are encountered especially when it is trained using full object templates. Therefore, we propose a new method called discriminative patches (d‐patches), which is a traffic sign detection (TSD) framework with occlusion handling capability. D‐patches are those regions of an object that possess the most discriminative features than their surroundings. They are mined during training and are used for classification instead of the full object templates. Furthermore, we observe that the distribution of redundant‐detections around a true‐positive is different from that around a false‐positive. Based on this observation, we propose a novel hypothesis generation scheme that uses a voting and penalisation mechanism to accurately select a true‐positive candidate. We also introduce a new Korean TSD (KTSD) dataset with several evaluation settings to facilitate detector's evaluation under different conditions. The proposed method achieves 100% detection accuracy on German TSD benchmark and achieves 4.0% better detection accuracy, when compared with other well‐known methods (under partially occluded settings), on KTSD dataset.

The vision‐based lane detection is an important component of advanced driver assistance systems and it is essential for lane departure warning, lane keeping, and vehicle localisation. However, it is a challenging problem to improve the robustness of multi‐lane detection due to factors, such as perspective effect, possible low visibility of lanes, and partial occlusions. To deal with these issues, the authors propose an improved lane hypothesis generation method using a reliable binary blob analysis. Most existing top‐view based methods focused on the lane model fitting, but they neglected the reliability of hypothesis generation and the effectiveness in challenging conditions. To cope with these shortcomings, the authors carried out vanishing point detection and inverse perspective mapping to remove the perspective effect from the road images. Then two‐stage binary blob filtering and blob verification techniques using classification are introduced to improve the robustness of lane hypothesis generation for lane detection. The experimental results show that the average detection accuracy on a new challenging multi‐lane dataset is 97.7%. The performance of the proposed method outperforms that of the state‐of‐the‐art method by 1.6% in detection accuracy on the Caltech lane benchmark dataset.

In this study, a novel and efficient technique is proposed for road vanishing point detection in challenging scenes. Currently, most existing texture‐based methods detect the vanishing point using pixel wise texture orientation estimation and voting map generation, which suffers from high computational complexity. Since only road trails (e.g. road edges, ruts, and tire tracks) would contribute informative votes to vanishing point detection, the Weber adaptive local filter is proposed to distinguish road trails from background noise, which is envisioned to reduce the workload and to eliminate uninformative votes introduced by the background noise. Furthermore, instead of using the conventional pixel‐wise voting scheme, the salient‐block‐wise weighted soft voting is developed to eliminate most of the noise votes introduced by incorrectly estimated pixel‐wise texture orientations, and to further reduce the computation time of voting stage as well. The experimental results on the benchmark dataset demonstrate that the proposed method shows superior performance. The authors’ method is about ten times faster in detection speed and outperforms by 3.6% in detection accuracy, when compared with a well‐known state‐of‐the‐art approach.

This study addresses the shortcomings of the dark channel prior (DCP). The authors propose a new and efficient method for transmission estimation with bright‐object handling capability. Based on the intensity value of a bright surface, they categorise DCP failures into two types: (i) obvious failure: occurs on surfaces that are brighter than ambient light. They show that, for these surfaces, altering the transmission value proportional to the brightness is better than the thresholding strategy; (ii) non‐obvious failure: occurs on surfaces that are brighter than the neighbourhood average haziness value. Based on the observation that the transmission of a surface is loosely connected to its neighbours, the local average haziness value is used to recompute the transmission of such surfaces. This twofold strategy produces a better estimate of block and pixel‐level haze thickness than DCP. To reduce haloes, a reliability map of block‐level haze is generated. Then, via reliability‐guided fusion of block‐ and pixel‐level haze values, a high‐quality refined transmission is obtained. Experimental results show that the authors’ method competes well with state‐of‐the‐art methods in typical benchmark images while outperforming these methods in more challenging scenarios. The authors’ proposed reliability‐guided fusion technique is about 60 times faster than other well‐known DCP‐based approaches.

Variations in road types and its ambient environment make the single image based vanishing point detection a challenging task. In this study, a novel and efficient vanishing point detection method is proposed by using random forest and patch‐wise weighted soft voting. To eliminate the noise votes introduced by background region and to reduce the workload of voting stage, random forest based valid patch extraction technique is developed, which distinguishes the informative road patches from the background noise. To prepare training data for the random forest, a training patch generation method is proposed, and a variety of road relevant features are introduced for training patch representation. Since the traditional pixel‐wise voting scheme is time consuming and imprecise, a patch‐wise weighted soft voting scheme is proposed to generate a more precise voting map and to further reduce the computational complexity of voting stage. The experimental results on the benchmark dataset show that the proposed method reveals a step forward in performance. The authors’ approach is about 6 times faster in detection speed and 5.6% better in detection accuracy than the generalised Laplacian of Gaussian filter based method, which is a well‐known state‐of‐the‐art approach.

In real‐world scenes, vehicles are frequently overlapped by other objects and various backgrounds. In this study, an effective method to detect such vehicles, especially those partially occluded by nearby vehicles or other objects is presented. The authors have developed a statistical approach to generate occlusion hypothesis and a new hypothesis verification method. To verify occlusion hypothesis, the verification method utilises geometric and likelihood information. In this way, both vehicle–background and vehicle–vehicle occlusions can be detected. No additional occlusion‐specific training is required. In addition, a median filter is applied to eliminate the noise in the patch scoring, and a union‐find algorithm is used to find the connected positive region in the binary map. A synthesised occlusion dataset is created to test the performance, and the experimental results on popular benchmarks indicate that the proposed method is effective and robust in recognising partially occluded vehicles.

The authors propose a novel and efficient method for single image dehazing. To accelerate the transmission estimation process, a block‐to‐pixel interpolation method is used for fine dark channel computation, in which the block‐level dark channel is first computed, and then the fine pixel‐level dark channel is obtained by a weighted voting of the block‐level dark channel to preserve edges and smooth out texture noise. This technique can be used for a direct transmission map generation without a computationally expensive refinement step. Since the dark channel prior (DCP) is not valid in bright (sky) regions, they propose an adaptive DCP modelled by a Gaussian curve that produces a more natural recovered image of the sky and other bright regions. In addition, a scaling method for transmission map computation is proposed to further accelerate the dehazing method. Through experiments, they show that the proposed adaptive block‐to‐pixel technique is about 30 times faster and produces improved recovered images than the well‐known state‐of‐the‐art DCP approach.

The control signal sharing while packing flip-flops and other instances in slices is a necessary constraint in the placement of instances in FPGAs. Global placement usually does not consider signal sharing. In this paper, we propose a control signal aware slice-level packing algorithm within the framework of window based legalization method to obtain an optimized legal layout, satisfying all constraints, after global placement. We select a target window with the highest number of overlaps. Then, we check the capacity of the target window and adjust its size to secure enough space required for legalization. Lastly, window based legalization takes three constraints into account: 1) Control Signal Sharing: Two Flip-Flops in a slice must share a single control signal in FPGA architecture. 2) CLB Architecture Matching: Instances should be placed within a half slice to minimize the routing requirement. 3) Slice Level Packing: Instances are packed into slices for effective utilization of available empty space within a window. The experimental results show that our algorithm performs better with 45% less block displacement and 10% less runtime with the same wirelength when compared to a previous well-known mixed size block greedy legalization method [1].

The idea of safe and smart vehicles has been thoroughly researched over the past decades to ensure drivers' safety from possibly dangerous situations. This paper presents a brief review of different applications of image processing and computer vision techniques in smart vehicles. To detect other on-road vehicles, researchers have approached the problem from various angles; with solutions ranging from active sensors like radar to passive sensors like cameras. Recently, researchers are working to create a panoramic 360 degree view of the vehicle's environment by merging different images from sides, rear and front of the car using passive sensors. There has also been work on constructing high resolution images from low cost, low resolution cameras, in order to reduce final cost of the system. In this paper, we have presented a new algorithm for mono-camera based vehicle detection systems, by incorporating different low level (edges) and high level features (Bag-of-features). To extract edge information flawlessly, we presented a new edge detection method, namely Difference of BiGaussian (DoBG). Experimental results show average 98.5% recognition rates, which is one of the best results achieved so far.

Silicon validation becomes difficult because of rapidly increasing complexity and operation speed of integrated circuits. When an error is found after a chip is fabricated, post-silicon repair is necessary. Full mask revision may significantly increase the cost and time-to-market. In this paper, we describe partial metal revision techniques in which only top-level metal layers are revised to fix ¿small¿ errors with minimal increase of the cost. When an error cannot be fixed by partial metal layer revision, full metal revision or full mask revision is necessary. However, frequently errors are small enough to be fixed by partial metal layer revision. Effective partitioning and pin-extension to top-level metal layers can significantly improve the repairability by using top-level metal revision.

Texture mapping is one of the techniques that express realism in three-dimensional (3-D) graphics. To produce high-quality images, various anisotropic filtering methods have been proposed for texture mapping. These methods require more texels than isotropic (trilinear) filtering method. In spite of increases to texture memory bandwidth, however, texture memory bandwidth is still a bottleneck of texture-filtering hardware. Consequently, an exact filtering method is required for good-quality images in a limited texture memory bandwidth. In this paper, we propose anisotropic texture filtering based on edge functions. Our method proposes an exact footprint-shape approximation with edge functions for generating weights. For real-time filtering, the weight plays a key role in effective filtering of the restricted texels loaded from memory. The normalized value of the edge function gives the distance relative to the contribution of texels to a final intensity. Calculating a Gaussian filter using this normalized value, generates a good weight. The quality of rendered images is superior to other anisotropic filtering methods with the same restricted number of texels. For images of the same quality, our method requires less than half the texels of other methods. Consequently, the improvement in performance is more than twice that of other methods. With low hardware overheads, our method can be implemented at a reasonable cost. In practice, the algorithm is demonstrated through VLSI implementation. The hardware, which is described by verilog and synthesized with a 0.35-/spl mu/m 3.3-V standard cell library, is operated at 100 MHz and it generates 100 M texture-filtered RGB pixel-color values per second.

One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is Phong shading. With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is amenable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table. This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size.

A new hierarchical layout vs. schematic (LVS) verification system has been developed for layout verification. It compares a hierarchical schematic netlist and a flattened layout netlist. The schematic hierarchy is restructured for consistent hierarchical matching and then the same hierarchy is built from the layout netlist. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm. Each subcircuit is found from the layout by using a modified SubGemini algorithm in bottom-up fashion. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage.

One of the most successful algorithms that bring realism to the world of 3D-image generation is Phong shading. But, Gouraud shading has been used instead of Phong shading because of per pixel computation and hardware costs. However, with continuous improvement of VLSI technologies and request for higher realism, real-time Phong shading will be the next technology-push in 3D graphics. Taylor series approximation is an algorithm of fast Phong shading algorithms that is appropriate for hardware implementation. But, the hardware implementation of this algorithm requires a large ROM table that induces an overhead in terms of hardware size. We reduced this overhead by minimizing the ROM table size while keeping visual quality through visual comparison. We minimized a large ROM table size of a uniform quantization method to 1/64 using an adaptive-compressed non-uniform quantization method. By minimizing the ROM table size, we could minimize the total hardware size to 1/56.

FPGAs are widely used for logic emulation, software acceleration, custom computing, and prototyping. The architecture (or the interconnect mechanism of a FPGA network) of an emulator has profound effect on the performance (speed) and efficiency (chip utilization) of the emulator. In this paper, several architectures of FPGA networks are suggested, and they are compared with other typical existing architectures by using the MCNC partition benchmark circuits. Experimental results show that tripartite network outperforms six other typical architectures both in performance and in efficiency. For this study, the propagation delay of a path is estimated by the number of hops (interchip connections) and the number of intrachip connections on the path, and thus it is independent of a specific FPGA type. To partition a given circuit into the given prerouted network of FPGAs, a new routability-driven partitioning algorithm is developed. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average, and that performance-driven partitioning is effective in reducing critical time delays.

No abstract available.

An efficient and effective optimization technique is developed for technology mapping of lookup table (LUT) based field programmable gate arrays. In our algorithm, minimal depth of a Boolean network is found and then the given cost function is minimized by "sweeping" nodes of the given Boolean network without increasing the depth. The sweeping allows an efficient search over a huge solution space since it utilizes the topological structure of the network. Optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that our approach is very promising. Typically our method, called SWEEP, produced the same depth for the 17 benchmark circuits tried as those of FlowMap which guarantees the optimum depth. Furthermore, SWEEP outperforms FlowMap by 17% in the total number of LUT's required to implement the benchmark circuits.>

A hierarchical placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimize the number of crossing nets while the objective of placement by simulated annealing is usually to minimize the total estimated wire-length. The combined placement algorithm can optimize both the routing density and the estimated wire-length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction, i.e., big groups of cells are placed at the beginning and leafcells are placed at the final level. Several standard-cell and sea-of-gates circuits are placed using the combined placement techniques and promising results are obtained when compared with those of several other placement methods.

Partitioning is an important step in the top-down design of large complicated integrated circuits. In this paper, a simple yet effective partitioning technique is described. It is based on the clustering of "closely" connected cells and the gradual enforcement of size-constraints. At the beginning, clusters are formed in the bottom-up fashion to reduce the problem size. Then the clusters are partitioned using several different parameters to find a good starting point. The best result achieved during the cluster partitioning is used as the initial solution for the lower level partitioning. The gradual constraint enforcement technique is used to cope with the local minimum problems. It allows cells or clusters to move with more freedom among the subsets during earlier iterations and thus may effectively find a near optimum solution. Several experimental results show that the new partitioning technique produces favorable results. In particular, the method outperforms the F&M method by more than 60% in the number of crossing nets on average.>

Zone-refining refers to a technique that forms a basis for layout compaction algorithms intermediate between one-dimensional (1-D) compactors and two-dimensional (2-D) placement techniques. An expanded zone in which 2-D refinement techniques are employed is repeatedly swept across the layout in different directions. The basic principle is reviewed and the computational complexity of zone refining is analyzed. The difficulties that had to be overcome in making the basic concept useful for compaction of integrated circuit layouts is discussed. One implementation is described, and some of the tradeoffs made and data structures used to obtain an efficient compactor are examined. The scope of possibilities for other implementations are discussed.>

A new heuristic two-dimensional symbolic layout-compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce the layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bounded by Ο(T1), where T1 is the run time of a typical one-dimensional compactor.

A new algorithm of allocating functional units and connections in the data path synthesis has been developed. The algorithm determines the types and numbers of both functional units and connections simultaneously based on their cost (i.e., area) obtained from the input technology data. The algorithm performs trade-off between the functional units and connections to produce data paths with minimal cost. The algorithm is adaptive to different technologies: if the cost of a functional unit changes or if a new functional unit becomes available, the algorithm produces a new data path optimized in the new environment. The algorithm has O(n3) timing complexity in the worst case, where n is the number of operations in the input problem. Experiments show that costs of data paths constructed by our algorithm are smaller than or as much as those by other published approaches.

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.>

For the macrocell design style and for routing problems in which the routing regions are irregular, two-dimensional routers are often necessary. In this paper, a new routing technique that can be applied for general two-layer detailed routing problems, including switchboxes, channels, and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear edges, the pins can be on or inside the boundaries of the region, and the obstructions can be of any shape and size. The technique is based on an algorithm that routes the nets in the routing region incrementally and intelligently, and allows modifications and rip-up of nets when an existing shortest path is "far" from optimal or when no path exists. The modification steps (also called weak modification) relocate some segments of nets already routed to find a shorter path or to make room for a blocked net. The rip-up and reroute steps (called strong modifiction) remove segments of nets already routed to make room for a blocked connection; these steps are invoked only if weak modification fails. The algorithm has been rigorously proven to complete in finite time and its complexity has been analyzed. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and on all the examples known in the literature the router has performed as well as or better than existing algorithms. In particular, Burstein's difficult switchbox example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II on all the channels available to us.

A new technique for 2-dimensional layout compaction of integrated circuits is presented. After a traditional one-dimentional precompaction step, the size of the layout is further reduced with a technique that bears a strong similarity to the technique of 'zone-refining' used in the purification of crystal ingots. Individual circuit components or small clusters of components are peeled off row by row from the precompacted layout, moved across an open zone, and reassembled at the other end of this zone in a denser configuration. In this process both coordinates of the moved components are altered and jogs are introduced in the connecting wires between them to produce the needed flexibility for placing components into optimal positions. The constraint graphs in both the x- and y-direction are used and updated concurrently.