Demo Data from EDBT 2026 / reviewers in the wild / expert
Hiroyuki Umimoto
dblp:89/5024
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 70% High-performance computing · 20% Integrated circuit design · 10% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › technology computer-aided design
process simulation |
0.0 | 2 | 1989 | Numerical modeling of nonplanar oxidation coupled with stress effects · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 SMART-P: rigorous three-dimensional process simulator on a supercomputer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Electronic design automation › technology computer-aided design
device simulation |
0.0 | 1 | 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Electronic design automation › technology computer-aided design › device simulation
MOSFET simulation |
0.0 | 1 | 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
High-performance computing
scientific computing systems |
0.0 | 2 | 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 SMART-P: rigorous three-dimensional process simulator on a supercomputer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Integrated circuit design
semiconductor device modeling |
0.0 | 2 | 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 SMART-P: rigorous three-dimensional process simulator on a supercomputer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
High-performance computing › scientific computing systems
supercomputer simulation |
0.0 | 2 | 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 SMART-P: rigorous three-dimensional process simulator on a supercomputer · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988 |
Methods — techniques the papers use, named apart from their topics
finite difference method · 0.0relaxation technique · 0.0coordinate transformation · 0.0generalized coordinate transformation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | SMART-II: a three-dimensional CAD model for submicrometer MOSFET'sabstractThe authors describe a three-dimensional CAD model for submicrometer MOSFETs. The model has been implemented in a three-dimensional process/device integrated simulator, SMART-II, using a supercomputer. The MOS device model for hot electron transport is based on a modified current relation including an electron temperature effect in an inhomogeneous field. The need for an improved mobility model in an inversion layer and an impact ionization model using the recent experimental data for the mean free path is discussed with emphasis on the numerical simulation for I/V characteristics of small-geometry MOSFETs from the threshold regime to the avalanche regime. It is found that this approach is effective in realizing a three-dimensional CAD model for 0.5- mu m MOSFETs. An application of the model reveals a three-dimensional effect of avalanche breakdown behavior in small-geometry MOSFETs.> Shinji Odanaka, Akira Hiroki, Kikuyo Ohe, Kaori Moriyama, Hiroyuki Umimoto |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 1989 | Numerical modeling of nonplanar oxidation coupled with stress effectsabstractThe study focuses on the numerical solution method based on a finite-difference approach with the coordinate transformation method for simulating the nonplanar oxide growth. A relaxation technique is introduced to incorporate the stress effect into oxidation kinetic equations maintaining numerical stability. In addition, for simulating the stress-dependent oxide growth, the role of the boundary condition at the free-oxide surface is discussed. The present method allows an accurate evaluation of the local stress distribution in nonplanar oxide structures and realizes the precise simulation of oxide shapes under the large stress effect. They are demonstrated in applications to both the LOCOS process with thick nitride film and the trench oxidation process, which strongly depends on the oxidation-induced stress at trench corners.> Hiroyuki Umimoto, Shinji Odanaka, Ichiro Nakao, Hideya Esaki |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1988 | SMART-P: rigorous three-dimensional process simulator on a supercomputerabstractA description is given of a three-dimensional process simulator, named SMART-P, that is based on the finite-difference approach to the supercomputer FACOM VP-100. To simulate the impurity redistribution and nonplanar structure in the Si/SiO/sub 2/ system, this simulator contains a three-dimensional oxidation model, an interaction model of impurities, a numerical model of interstitial-assisted oxidation-enhanced diffusion, and other process models. The numerical process modeling in the Si/SiO/sub 2/ system is described. The three-dimensional process modeling CAD (computer-aided design) has been realized by using efficient numerical algorithms based on the generalized coordinate transformation method. The capabilities of this simulator have been demonstrated in applications relating to both local oxidation of silicon (LOCOS) and trench-isolated 0.5 mu m MOSFET structures.> Shinji Odanaka, Hiroyuki Umimoto, Mutsuko Wakabayashi, Hideya Esaki |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |