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G. F. Taylor

dblp:89/5079 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › signal processing accelerator
FFT processor		 0.011988
An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor · IEEE Trans. Computers 1988
Processor architecture and microarchitecture › pipelining
parallel-pipeline architecture		 0.011988
An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor · IEEE Trans. Computers 1988
Hardware accelerators and domain-specific architectures
signal processing accelerator		 0.011988
An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor · IEEE Trans. Computers 1988

Methods — techniques the papers use, named apart from their topics

pipelining · 0.0butterfly processing · 0.0
YearPublicationVenuePosition
1988 An Architecture for a Video Rate Two-Dimensional Fast Fourier Transform Processor
abstract
A description of an architecture capable of computing two-dimensional fast Fourier transforms on a 256*256 pixel image at a rate of 30 images per second is presented. The architecture consists of a small number of basic building blocks which may be repeated to yield any desired performance. To achieve video rate performance, 16 butterfly processors, arranged as four coupled clusters of four processors each, and nine working memories are required. Because of the parallelism and pipelining used in the design, the system clock needed to achieve this high level of performance is only 240 ns.>
G. F. Taylor, Randy H. Steinvorth, John F. McDonald 0001
 IEEE Trans. Computers1
1985 An Architecture for a Video Rate Fuzzy Golay Processor
Randy H. Steinvorth, G. F. Taylor, John F. McDonald 0001, T. Hunter
 ICPP2