3D phase-change memory (3D PCM) is one of the primary candidates for next-generation memory technologies. To enhance its endurance, a subthreshold read operation has been proposed. However, this operation exhibits extremely low read currents, which are further compromised by a considerable amount of leakage currents, thereby deteriorating the sensing margin. To address this challenge, this paper proposes a subthreshold adaptive-reference leakage-compensation sensing scheme for 3D PCM. The reference current is address-adaptive, and the leakage current is sampled and compensated accurately. Evaluation results demonstrate significant improvements in the proposed circuit. The sensing margin is increased by up to 46.7% and 34.7% across different half-selected cell statuses and addresses, respectively, compared to the conventional leakage-compensation sensing scheme. Moreover, the read endurance is increased by$51\times $, compared to the conventional read operation.

In this article, a power-on-reset (POR) circuit with accurate trigger-point voltage and ultralow typical quiescent current for emerging nonvolatile memory (NVM) is presented. To keep the trigger-point voltage from the effect of process, voltage, and temperature (PVT) and supply ramp rate variations, low-cost current generators and a current comparator are adopted with brown-out detection (BOD). A protection circuit is utilized for correct operations in different BOD events. Meanwhile, delay blocks are utilized to generate reliable pulse signals that are less influenced by temperature and supply ramp rate. The simulation results show that the trigger-point voltage is 2.08 V with a temperature coefficient (TC) of 81.8 ppm/$^{\circ}$C and a deviation to the ramp time of 9.91% for a wide ramp time range from 10$\mu $s to dc. In addition, the reset duration time of the POR pulse is also reliable. The proposed POR circuit designed in the 55-nm CMOS process consumes only 0.65-nA typical quiescent current and 59$\times$146$\mu $m area, which is suitable for emerging NVM systems.

In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback loops, ensuring complete resilience to quadruple-node upsets (QNUs). Each Sim comprises ten CMOS transistors and a clocked inverter. Notably, C-element (CE) and dual interlocked storage cell (DICE) modules are not employed in this circuit, resulting in a small area and low power consumption. The simulation results verify the complete QNU self-recoverability and cost-effectiveness of this design. Compared with the existing radiation-hardened QNU resilient latches, the LCQRL latch demonstrates significant improvements in area, power consumption, and area-power–delay product (APDP) by 47.8%, 63%, and 75.5%, respectively. Furthermore, it exhibits low sensitivity to process, voltage, and temperature (PVT) variations.

3-D cross-point Phase change memory (PCM) is one of the most promising next-generation nonvolatile memory for storage-class memories., and the subthreshold sensing strategy can effectively improve its limited endurance. For the first time, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function. Based on this model, we analyze the device/array/circuit parameters setting requirements for subthreshold sensing. The bit line voltage and the array should be less than 2.96V and 2k, respectively. The sensing time of the 512b array should be longer than 220ns. A large selected cell current$(\mathbf{I}_{\mathbf{c}\mathbf{e}\mathbf{ll}})$difference is always accompanied by a large leakage current$(\mathbf{I}_\mathbf{leak})$difference, which severely limits array size. The bias voltage$(\mathbf{V}_{\mathbf{b}\mathbf{i}\mathbf{a}\mathbf{s}})$adjustment scheme could increase the array size, but also the power consumption. The leakage current compensation scheme should adjust the compensation current dynamically as the variation of$\mathbf{I}_{\text{cell}}$is large.

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

For the first time, dynamic read performances of 1-selector-1-resistor (1S1R) memory arrays are enhanced by rational design of bias schemes. We use dynamic analyses to assess chip dynamic performances with circuits, arrays, bias schemes, and device parameters. The high voltage variation of half-selected cells on the bit line is found to result in a long read access time and a high peak read current, in the conventional V/2 bias scheme. To deal with this problem, we propose a 2V/3 read bias scheme with its voltage variation of half-selected cells on the bit line decreased from V/2 to V/3. As a result, 41.7% and 28.74% reduction in maximum and stable values of reset read current, respectively, a 29.04% reduction in sensing time, and a 37.24% increase in read margin are achieved, compared with conventional bias schemes. In addition, read errors are reduced to zero significantly for a sensing circuit. The proposed scheme also avoids excessive leakage in unselected devices and supports a single bit read in a subarray, which is suitable for 3-D memory.

As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept pace with the development. In this article, focusing on specific PCM faults and others, an enhanced march test algorithm is proposed to achieve 100% fault coverage and diagnostic accuracy in bit-oriented PCM. The proposed algorithm is then converted for word-oriented PCM and equipped with capability to detect potential intraword impact. In addition, to reduce the dependence of memory test on the external devices, a novel storage scheme of fault information is devised. Through the modeling and simulation in C-language, this method is proven to improve the probability of finding the predefined fault-free regions in the tested memory. Finally, combining the enhanced test algorithm and the novel storage scheme, a built-in self-test (BIST) march test scheme is proposed, realizing the independent test of PCM without any external equipment. By comparison, the result of experiments, which are performed with C-language, proves that the proposed test scheme not only increases the fault coverage and diagnostic accuracy, but also reduces the additional area overhead.

The emerging memory technologies, such as phase change memory (PCM), provide chances for highperformance storage of I/O-intensive applications. However, traditional software stack and hardware architecture need to be optimized to enhance I/O efficiency. In addition, narrowing the distance between computation and storage reduces the number of I/O requests and has become a popular research direction. This paper presents a novel PCMbased storage system. It consists of the in-storage processing enabled file system (ISPFS) and the configurable parallel computation fabric in storage, which is called an in-storage processing (ISP) engine. On one hand, ISPFS takes full advantage of non-volatile memory (NVM)’s characteristics, and reduces software overhead and data copies to provide low-latency high-performance random access. On the other hand, ISPFS passes ISP instructions through a command file and invokes the ISP engine to deal with I/O-intensive tasks. Extensive experiments are performed on the prototype system. The results indicate that ISPFS achieves 2 to 10 times throughput compared to EXT4. Our ISP solution also reduces the number of I/O requests by 97% and is 19 times more efficient than software implementation for I/O-intensive applications.

A 16-Mb mask read-only memory (ROM) chip based on a novel diode structure is proposed. The diodes are constructed by buried n-type implantation layer and heavily doped p-type diffusion layer. With dual-trench isolation process and borderless contact scheme, the diode array can realize ultrahigh density. The fabricated mask ROM chip using 40-nm CMOS bulk technology is wired with three levels of metal, only two levels for diode arrays. The effective diode size is as small as 0.017 μm2, which is the smallest bitcell of commercial mask ROM products in the world, to our best knowledge. The physical array density can achieve approximately 0.0225 mm2/Mb. Test results indicate that chip standby leakage current is c1 μA at 25 °C and c3.5 μA at 85 °C with 2.5 V supply voltage. Array standby leakage is c6.25 μA/Mb at 25 °C and c18.75 μA/Mb at 85 °C with 2.5 V supply voltage.