Li Zhang 0038

dblp:89/5992-38 · DBLP profile ↗
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7ranked-venue papers
1as first author
4since 2021 · last 2023
0000-0003-4277-0591ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 1 first-author · 4 since 2021
YearPublicationVenuePosition
2023 Improved Repetitive Control with Enhanced Active Damping Method for 400Hz Inverter
abstract
Since the harmonic frequency of 400Hz inverter is relatively high, it is difficult to eliminate the low-order harmonics with the traditional dual-loop control. Aiming at achieving zero steady-state error and enhancing the ability to suppress harmonics, the plugged-in repetitive control (RC) with the damping-based notch filter (DNF) is proposed. The DNF not only ensures the high open-loop gain at harmonic frequencies, but also facilitates the stability identification by ‘the two unit circles’. As the magnitude/phase-frequency behavior of the RC control plant is anticipated to be characterized by OdB and 0 degree, the internal current loop is regulated by the elaborated active damping loop with phase compensation. As the minimal-phase behavior is guaranteed, the harmonics around the resonance frequency$\boldsymbol{f}_{\mathbf{r}}$is well suppressed without threatening the stability of the RC-based system. Experimental results finally validate that the total harmonic distortion (THD<1%) is reduced by the elaborated repetitive control strategy.
Chunyang Wu, Li Zhang 0038, Shaojun Xie, Shian Guo
IECON3
2023 A Common-Mode Voltage Reduction DPWM Scheme for Three-Phase Three-Level Inverters with Unbalanced Neutral-Point Voltage
abstract
High-frequency variation of the common-mode voltage (CMV) causes severe leakage current and electromagnetic interference (EMI) in photovoltaic (PV) generation and motor drive systems. This paper proposes a discontinuous PWM (DPWM) to reduce CMV for three-phase three-level inverters under different NP voltage conditions. Firstly, the relationship between the CMV and NP voltage is revealed. Then, the switching-state sequence is optimized to reduce the magnitude and frequency variations of the CMV. Furthermore, since the switching state of one phase is clamped at each switching cycle, the switching loss is also reduced. Finally, a 6-kW inverter prototype is built, and experimental results show that the proposed scheme features lower CMV, lower leakage current, and higher efficiency.
Li Zhang 0038, Yuhang Zou, Yan Xing 0001, Huizi Zhuge, Wenyi Mo, Zhongshu Zheng
IECON1
2023 Full Grid Voltage Feedforward for Hysteresis Current Control Critical Mode LCL-Type Grid-Tied Inverters
abstract
Hysteresis current control is considered an effective method to achieve full power range zero-voltage-switching (ZVS) operation and good gird current quality of the critical mode (CRM) LCL-type grid-tied inverter. However, with the large-scale grid connection of distributed power generation systems (DPGS), the control performance of the LCL-type grid-tied inverter is seriously challenged by the large number of harmonics contained in the point of common coupling (PCC). In this paper, by combining the physical interpretation of the full grid voltage feedforward (GVF) and the physical model of the hysteresis current control (HCC) CRM LCL-type grid-tied inverter, a full GVF scheme is proposed for improving the grid current THD of the single-phase HCC-CRM LCL-type grid-tied inverter. All harmonics caused by the distorted grid voltage can be significantly suppressed by feeding forward the derivative term of the grid voltage to the hysteresis-band reference. A 1-kW single-phase LCL-type grid-tied inverter is built, and experiments are conducted to verify the effectiveness of the proposed strategy.
Zhongshu Zheng, Li Zhang 0038, Zhengzi Lei
IECON2
2023 A THD Improving Method for DPWM-Based Three-Phase Three-Level Inverters with Unbalanced Neutral-Point Voltage
abstract
Neutral-point (NP) voltage imbalance causes severe alternating output current distortion in three-phase three-level inverters when conventional discontinuous PWM (DPWM) schemes are employed. Existing improved DPWM schemes can not achieve low total harmonic distortion (THD) and simple digital implementation simultaneously. In this paper, a pulse-width compensation (PWC) scheme is proposed to improve the THD performance of DPWM-based three-level inverters under unbalanced NP voltage conditions. By using the proposed PWC scheme, the pulse width of the bridge-leg voltage of the unclamped phases is compensated according to the NP voltage. As a result, the fundamental component of the bridge-leg voltage is not affected by the NP voltage, and the alternating output current distortion is improved. Finally, a 6-kW inverter prototype is built, and experimental results show that the proposed PWC scheme can achieve low THD and simpler digital implementation than the existing improved DPWM scheme.
Yuhang Zou, Li Zhang 0038, Huizi Zhuge, Yan Xing 0001, Zhongshu Zheng, Yiding Wu
IECON2
2019 Dual-loop Control for Three-phase Vienna Rectifier with Duty-ratio Feedforward
abstract
As Boost-type topology, three-phase Vienna rectifier has the inherent problem of increasing output voltage at partial load. In this paper, a duty-ratio feedforward strategy based on dual-loop control is proposed to solve this problem. The comparison between a three-phase three-wire system and a three-phase four-wire system reveals that the main feature of the former is the zero-sequence component, which will not affect THD. It provides a theoretical basis for calculating three-phase feedforward respectively and carry it out in abc-domain. The feasibility of duty-ratio feedforward in other coordinate systems has also been demonstrated. Finally, the simulation and experimental results are given, which are compared with the commonly used grid-voltage feedforward in the dq-domain, to verify that the proposed feedforward strategy can not only operate stably at partial load, but also optimize THD to a certain extent.
Chuanhao Ji, Li Zhang 0038, Baolin Chen, Yan Ming, Yan Xing 0001, Xudong Ma
IECON2
2018 A Semi-Two-Stage H5 Inverter with Improved Efficiency and Low Leakage Current
abstract
A semi-two-stage transformerless PV grid-tied inverter based on H5 is proposed in this paper. By introducing the front-end Boost converter, the PV module and the output of the front-end Boost can be used as two different inputs of the H5 converter respectively. Therefore, the proposed topology can operate in a wide input range and part of the PV module power can be transmitted to the utility grid directly without being transferred through the path of the front-end Boost converter. The efficiency can be higher than that of the conventional two-stage H5 inverter. A modulation strategy for this topology is presented and analyzed in detail. The common-mode (CM) voltage varies with a low frequency which results in a low leakage current. An experimental prototype is built to verify the effectiveness of the proposed topology and modulation strategy.
Li Zhang 0038, Yan Xing 0001, Haibing Hu
IECON2
2018 A Dual-Buck Inverter with H5 Configuration for Photovoltaic Grid-tied Applications
abstract
In order to solve the problem of leakage current in the topology of transformerless photovoltaic (PV) grid-connected inverter, this paper proposes a high reliability dual-buck inverter using super junction MOSFET based on a conventional H5 topology. The PV side and the grid side are decoupled during freewheeling modes, leakage current is suppressed. Further, the independent diode with pretty good performance is beneficial to achieve higher efficiency. The dual-buck structure eliminates the shoot-through issue, which enhances system reliability and improves grid-tied current quality. Finally, it is verified by building a 1kw experimental prototype.
Yongqiang Hao, Li Zhang 0038, Fengkai Jiang
IECON2