EDBT 2026 Demo / reviewers in the wild / expert
Yuguang Wu
dblp:89/6136
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 1 | 1995 | Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches · IEEE Trans. Parallel Distributed Syst. 1995 |
Memory systems › cache
multiprocessor cache |
0.0 | 1 | 1995 | Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches · IEEE Trans. Parallel Distributed Syst. 1995 |
Memory systems › cache › cache organization
set-associative cache |
0.0 | 1 | 1995 | Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches · IEEE Trans. Parallel Distributed Syst. 1995 |
Memory systems
cache coherence |
0.0 | 1 | 1995 | Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches · IEEE Trans. Parallel Distributed Syst. 1995 |
Methods — techniques the papers use, named apart from their topics
trace-driven simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | Stack Evaluation of Arbitrary Set-Associative Multiprocessor CachesabstractWe propose a simple solution to the problem of efficient stack evaluation of LRU multiprocessor cache memories with arbitrary set-associative mapping. It is an extension of the existing stack evaluation techniques for all set-associative LRU uniprocessor caches. Special marker entries are used in the stack to represent data blocks (or lines) deleted by an invalidation-based cache coherence protocol. A method of marker-splitting is employed when a data block below a marker in the stack is accessed. Using this technique, one-pass trace evaluation of memory access trace yields hit ratios for all cache sizes and set-associative mappings of multiprocessor caches in a single pass over a memory reference trace. Simulation experiments on some multiprocessor trace data show an order-of-magnitude speed-up in simulation time using this one-pass technique.> Yuguang Wu, Richard R. Muntz |
IEEE Trans. Parallel Distributed Syst. | 1 |