In accordance with the resent advancement in Internet of Things (IoT), the needs for IoT experiment platform have been ever increasing. IoT system consists of various technologies such as networking, sensor controller, edge-side computing, server-side big data collections, analysis and their visualizations. An experimental environment that can handle the development and experiments of such an IoT system become important. In the IoT system, a highly flexible system structure for applications using Field Programmable Gate Array (FPGA) is required. The authors propose the Remote Laboratory System for handling IoT experiments in the Cyber Laboratory, which is an educational FPGA-based remote laboratory for under-graduate university students. It enables not only to use available board-level small computers but also to use FPGA boards for prototyping IoT edges. It can also organize the IoT cloud-server side programs in the hybrid cloud. The FPGA based edge-side computing approach can have much more freedom and flexibility to implement various sensor controls those can be customized for specific IoT applications. The use of free micro-processor IP-core and re-organizing the available FPGA CAD design platform allow us to reduce the burden of design and implementation efforts for the construction of new Cyber Laboratory to accommodate IoT designs and experiments. It also contributed to reduce the students' amount of efforts to conduct their own IoT design and experiments, where students are required to have various skills in Information Technologies (IT): hardware design, edge-side computing, server-side computing, networking and infrastructure construction. The use of the Docker container/Swarm and the Docker File contributed to construct their own IoT experiment platforms for every student automatically, in the form of "Infrastructure as Code". Furthermore, these separately designed IoT experiment platforms can be combined to conduct a group of group experiment simultaneously. The paper showed the Cyber Laboratory's usefulness and applicability for IoT kinds of Remote experiments.

The paper proposes a cyber laboratory in the form of a hybrid cloud, where the actual laboratory and the remote laboratory are combined. At the existing physical experiment laboratory, the limitation of the number of experimental devices for FPGA hardware design course resulted in platform usage congestions and extended laboratory hours. Migration to the cloud should be the natural solution. However, existing devices such as FPGA evaluation devices and Logic analyzers became obstacles to migrate to public clouds. The proposed system combines an On-Premise private cloud organized by laboratory platforms to perform device dependent services, and a public cloud where remaining design, development and evaluation stages, are carried out in the form of a PaaS (Platform as a Service). The design and experiment tasks should be modified accordingly to accommodate CAD tools in the set of the Web Services. Existing faculty database server and educational support system combine the private cloud, the public cloud and the faculty servers, in a seamless way. Students can migrate to and from laboratories at any design stages. As the device dependent tasks have been implemented in the Web Services, efficient sharing of platforms can be achieved in space and time sharing fashions. The public cloud ensures a scalable increase and decrease in server machines according to the student usages and seasonal load changes. The laboratory managing software takes care of the allocation and migration of student Virtual-Machines between the On-Premise private cloud and the public cloud. It can also accommodate the BYOD (Bring Your Own Device) style student usage, by preparing three different access methods: student side BYOD applications, the Web services and remote desktop connections.

Cyber Laboratory for FPGA-based logic design course is underdevelopment. It tries to realize real-life logic design and FPGA-run environments and to offer real-life experiences for students, irrelevant of whether they are at remote sites or at actual sites. It combines actual laboratories and remote laboratories to achieve efficient sharing of FPGA design/ evaluation platforms and efficient use of student PCs. It reduces the waiting time for platforms and improves the interactive performance. The use of the cloud storage realizes a smooth and seamless transferring of design files and experiment results. The hardware logic design course consists of the six stage design flow: logic design entry, logic simulation, Verilog-HDL logic synthesis, FPGA compilation, actual FPGA-run and post analysis. The student PC works as a remote desk top mode, when the laboratory platform is served as the actual laboratory mode, where the physical platform has to be used in an exclusive way. The student can enjoy comfortable design environments, but the total number is limited up to the available platforms. When the number of students exceeds the number of platforms, the use of remote laboratory services modes enables to accommodate many students to perform their experiments concurrently in almost the same way as the actual laboratory. The FPGA platforms accept the Verilog-HDL synthesis services and the FPGA setup/ run services in the form of the Web services. Requests are serviced in time and space division fashions. As for the time consuming tasks, i.e. the logic design entry/ simulation and FPG compilation, these tasks can be run on student PCs in order to off-load the platforms' works. So an efficient sharing of platforms can be achieved. This can also improve interactive performance especially at design entry/ simulation time. At the final post analysis phase, students can remotely investigate the logic analyzer measured results which were obtained at the previous run phase. The modern PC-based logic analyzer allows such measurements and stores them in the cloud storage for students to replay the experiments on their own PCs. As design, configuration and result files are transferred via cloud storage, it becomes easy to migrate among different laboratory modes in the Cyber laboratory.

New top-down eLearning tools for hardware logic design courses using the cellular methods are presented that enable students to keep focusing on their primary interests so that they can achieve complex logic circuits design successfully. In a modern logic design classroom, hardware description languages such as VerilogHDL are mostly used to describe circuits for FPGAs. The circuit in each module is described in VerilogHDL and the entire circuit is implemented by combination of designed modules. These HDL descriptions are wrapped in XML and enriched by a specially extended XML vocabulary, in order to share designed modules among learners on the Web. Although XML gives us a common and convenient Web framework, it becomes difficult to verify, validate, and maintain conformance among designed modules if the system becomes very large. To overcome this problem, we employed the cellular models that ensure the consistency among design modules and support a top-down design methodology. The proposed top-down eLearning tools can generate these circuit design data, distribute them to the learner, and manage the design database. The circuit design data wrapped in XML vocabulary are offered to the learner as a self-learning material of the courseware using the top-down (i.e. goal-oriented) method, according to the demand.

The authors describe a novel parallel detailed router named PROTON (parallel router on a parallel machine) with various new features. These features include: a parallelized line search algorithm based on parallel breadth first search; extraction of a higher degree of parallelism by simultaneous routing of multiple nets using the result of the global router; a parallel router on a quasi-shared-memory based MIMD parallel machine; and a detailed router supporting multilayer channelless gate arrays with complex industrial design rules. PROTON is implemented on an MIMD parallel machine named Cenju, which consists of 64 microprocessors. In order to improve routing speed, PROTON incorporates two levels of parallelism, namely magnet parallelism and net level parallelism. A speedup of 43 times has been achieved using 64 processors for a medium-scale channelless gate array (1537*1790 grids, 12591 pin pairs).>

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs.>

This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.

The architecture of a proto-type functional level simulator element of a massively parallel machine (MAN-YO) designed for logic design automation is presented. At functional level, hardware systems are described in a hardware description language, FDL. The FDL description is compiled into stack oriented intermediate language instructions. Communicating with other gate level/block level/ functional level processors, each functional simulator interprets the compiled instructions and simulates various circuits using 4-value logic. In order to realize high speed processing of 4-value logic/arithmetic operations, the functional simulator utilizes low-level parallelism realized by 3 ALUs which are controlled by the different fields of a long horizontal type microinstruction. By utilizing low-level parallelism at processor level, as well as processor level parallelism, high speed execution of mixed level simulation becomes possible. The system also provides further performance enhancement by compiling often used FDL macros into microcode. This paper describes an outline of the MAN-YO (Japanese for ten thousand leaf-nodes in the processor tree), a brief description of FDL, and the architecture of the functional level simulator element (called FDLPE). A rough performance based on the current design is also described.