We present a method for SPICE model parameter extraction for a bipolar transistor in the active and quasisaturation modes. It uses the capabilities of the BIPOLE3 simulator to enhance the optimization procedure. Comparisons are made between the Gummel-Poon, the VBIC95, and the SGS-Thomson Microelectronics SPICE model results for I/sub C/(V/sub BE/), I/sub B/(V/sub BE/), /spl beta/(I/sub C/), f/sub T/(I/sub C/), and I/sub C/(V/sub CE/) characteristics.

A new approach to modeling the characteristics of a real three-dimensional bipolar transistor (BJT) is presented. It is based on the joint use of the BIPOLE program for calculating the intrinsic and emitter sidewall BJT characteristics and a special code RBCALC for calculating the two-dimensional potential distribution in the base region. The results presented show the importance of accounting for the third dimension for accurate calculation of some important BJT characteristics.>

Recent advances in integrated circuit technology have involved process development, device, and circuit optimization under scaled design rules. It is advantageous to be able to simulate the overall circuit performance under different conditions. A simulator which performs this task at the logic gate level becomes important. This paper describes such a simulator for digital bipolar integrated circuit families: WATPAC. WATPAC uses the process simulator SUPREM, the device simulator BIPOLE, and the circuit simulator WATAND. The input parameters to WATPAC are entered interactively. These consist of fabrication process parameters, layout design rules, a specification of the logic family, and a WATPAC predefined logic function. The WATPAC output consists of overall circuit performance data for the simulated function block. The output of WATPAC also includes the intermediate outputs of the process simulator, device simulator, and the circuit simulator.