A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.

It is shown that if a 4-by-n binary matrix has four distinct even-parity rows such that each column has exactly two 0's and two 1's, then there exists a totally self-checking even-parity checker that is tested by the four rows of this matrix. The utility of this result in designing self-testing embedded parity checkers is described.

A new design for a totally self-checking 1-out-of-n checker is presented. A comparison with other existing methods [1], [10] is given. It is shown that for many practical values of n the new scheme requires less hardware and/or is faster than the other methods. The entire checker can be tested by applying all of the n possible 1-out-of-n inputs.