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Parviz Palangpour

dblp:89/6815 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 1 first-authorSystems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Integrated circuit design · 23%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Machine learning › Efficient and distributed learning
model quantization
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Machine learning › Efficient and distributed learning › model deployment
quantized model deployment
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Integrated circuit design
system-on-chip
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020

Methods — techniques the papers use, named apart from their topics

quantization · 0.9SIMD architecture · 0.9
YearPublicationVenuePosition
2020 High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product
abstract
Demand for high performance deep learning (DL) inference in software applications is growing rapidly. DL workloads run on myriad platforms, including general purpose processors (CPU), system-on-chip (SoC) with accelerators, graphics processing units (GPU), and neural processing unit (NPU) addin cards. DL software engineers typically must choose between relatively slow general hardware (e.g., CPUs, SoCs) or relatively expensive, large, power-hungry hardware (e.g., GPUs, NPUs). This paper describes Centaur Technology's Ncore, the industry's first high-performance DL coprocessor technology integrated into an x86 SoC with server-class CPUs. Ncore's 4096 byte-wide SIMD architecture supports INT8, UINT8, INT16, and BF16 datatypes, with 20 tera-operations-per-second compute capability. Ncore shares the SoC ring bus for low-latency communication and work sharing with eight 64-bit x86 cores, offering flexible support for new and evolving models. The x86 SoC platform can further scale out performance via multiple sockets, systems, or third-party PCIe accelerators. Ncore's software stack automatically converts quantized models for Ncore consumption and leverages existing DL frameworks. In MLPerf's Inference v0.5 closed division benchmarks, Ncore achieves 1218 IPS throughput and 1.05ms latency on ResNet-50v1.5 and achieves lowest latency of all Mobilenet-V1 submissions (329μs). Ncore yields 23x speedup over other x86 vendor percore throughput, while freeing its own x86 cores for other work. Ncore is the only integrated solution among the memory intensive neural machine translation (NMT) submissions.
G. Glenn Henry, Parviz Palangpour, Michael Thomson, J. Scott Gardner, Bryce Arden, Jim Donahue, Kimble Houck, Jonathan Johnson, Kyle O'Brien, Scott Petersen, Benjamin Seroussi, Tyler Walker
ISCA2
2008 Hardware implementations of Swarming Intelligence - a survey
abstract
Swarming intelligence (SI) is the property of a system whereby the collective behaviors of (unsophisticated) agents interacting locally with their environment cause coherent global patterns to emerge. Because there are no central processing requirements, SI is ideal for parallelization, which lends it well to hardware implementations in many inexpensive processors. Several implementations in hardware that exploit this property for rapid calculation and inexpensive construction are highlighted in this paper to provide a good starting point for developing hardware platforms for SI algorithms.
Cameron Johnson, Ganesh K. Venayagamoorthy, Parviz Palangpour
SIS3
2006 Recurrent Neural Network Based Predictions of Elephant Migration in a South African Game Reserve
abstract
A large portion of South Africa's elephant population can be found on small wildlife reserves. When confined to enclosed reserves the elephant densities are much higher than observed in the wild. The large nutritional demands and destructive foraging behavior of elephants threaten rare species of vegetation. If conservation management is to protect threatened species of vegetation, knowing how long elephants will stay in one area of the reserve as well as which area they will move to next is essential. The goal of this study is to train a recurrent neural network (RNN) to continuously predict an elephant herd's next position in the Pongola Game Reserve. Accurate predictions would provide a useful tool in assessing future impact of elephant populations on different areas of the reserve. The particle swarm optimization (PSO) algorithm is used to adapt the weights of the neural network. Results are presented to show the effectiveness of RNN-PSO for elephant migration prediction.
Parviz Palangpour, Ganesh K. Venayagamoorthy, Kevin Duffy
IJCNN1