Modern FPGAs' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multi-core processor, the recently announced Cell Broadband EngineTM1 offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing devices together in a reconfigurable blade and we describe its architecture, memory system and abundant interfaces. On the reconfigurable blade it is desirable that the FPGA devices can be partially reconfigured at run-time. This paper presents the dynamic partial reconfiguration (DPR) technique and its design flow for the reconfigurable blade. We report our experimental results of the blade doing partial reconfiguration. DPR allows the reconfigurable blade to be a powerful, run-time changeable computing engine. A sample application is presented that was both simulated for the Cell processor and dynamically loaded to run on the FPGA.

The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks. The particular behavioral specification we consider is an intuitive user-created network diagram of sensor blocks, each block having a pre-defined combinational or sequential behavior. We synthesize this specification to a new network that utilizes a minimum number of programmable blocks in place of the predefined blocks, thus reducing network size and hence network cost and power. We focus on the main task of this synthesis problem, namely partitioning pre-defined blocks onto a minimum number of programmable blocks, introducing the efficient but effective PareDown decomposition algorithm for the task. We describe the synthesis and simulation tools we developed. We provide results showing excellent network size reductions through such synthesis and significant speedups of our algorithm over exhaustive search while obtaining near-optimal results for 15 real network designs as well as nearly 10000 randomly generated designs.

We describe the development of a set of embedded system building blocks, known as eBlocks. An eBlock network can be viewed as a basic form of sensor network that can be developed by non-programming engineers, scientists, and others. Each eBlock has a defined function, either one of a few predefined combinational or sequential functions, a custom-programmed function defined by an automated tool, or by user with programming skills. A user creates an application simply by connecting blocks, and possibly performing simple configuration via dials and switches. We have built over 100 physical eBlock prototypes, and tested their usability with over 100 non-programming users to date. We will describe the architecture of the blocks, including design tradeoffs we considered and the benefit of an exploration tool that we developed to help optimize the power and performance of the design. We have also built a graphical eBlock simulator that users can utilize to quickly build and test systems before deployment, and that we have used in experiments with over 300 non-programming users to help us define intuitive block functions and interfaces. We will describe the simulator architecture, as well as a tool that automatically converts a user's eBlock network into a much smaller network of programmable blocks with accompanying automatically generated programs.