Local defect patterns (LDP) in wafer maps are usually induced by problems in the manufacturing process. Therefore, defect pattern recognition is useful for root cause analysis, which is very important for yield optimization. Machine learning (ML) based methods can achieve good LDP recognition rate. In general, these techniques are designed to identify spatial patterns, which may not directly linked to the root cause. Besides, ML methods are more time-consuming because of the training process. In this paper, we propose to apply a rule-based method for LDP classification such that the recognized patterns are explainable. Experimental results show that the proposed method achieves roughly the same level of accuracy as other ML methods while the exaction time is much faster.

We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

The scratch defect type is difficult to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. The recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method. The method is validated by real products. Experimental results show that the average recall, precision and accuracy achieved by the proposed method are 97.22%, 98.81%, and 99.92%, respectively. Furthermore, the proposed method is based on image processing techniques alone with low processing time. In contrast to machine-learning based methods, there is no need to train a complicated prediction model.

Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a grid pattern recognition methodology taking into account both partial and hidden grid patterns. Hidden defective dies are dies in the grid contour that pass wafer test. However, such dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the potential defective dies in hidden grid patterns and mark them as faulty. As a result, the reliability of products and test cost can be significantly improved. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. A five-phase method is developed to enhance wafer maps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and also achieve 96.45% by Extremely Randomized Trees for all nine common wafer defect types averagely.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

Wafermap defect pattern detection and diagnosis provide useful clue to yield learning. However, most wafermaps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Specially, recognizing scratch and line types of defect patterns is a challenging problem for process and test engineers and it takes a lot of manpower to identify such patterns, as potential defective dies may exist on the scratch contour and become discontinuity points. However, such potential defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in potential scratch patterns and mark them as faulty. As a result, the quality and reliability of products can be significantly improved and cost of final test can be reduced. In this paper, we propose a systematic methodology to search for potential scratch/line defect types in wafers. A five-phase method is developed to enhance wafermaps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve more than 89% prediction accuracy for scratch/line types, and higher than 94% for all common wafer defect types.

On-chip interconnect structures become much more complicated and dominate system performance in multicore system-on-chips. Oscillation ring (OR) test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that both 100% fault coverage and the optimum diagnosis resolution for various fault models are achievable. The cost of OR test is decided by the number of test sessions required to form all the rings. Previous ring generation algorithm tries to generate long rings that usually cannot be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this brief, we study techniques to generate rings that can be tested concurrently, so that the overall test time can be reduced significantly.

An interconnect-driven layout-aware multiple scan tree (MST) synthesis methodology for 3-D integrated circuits (ICs) is proposed. MSTs, also known as scan forest, greatly reduce test data volume and test application time in system-on-a-chip testing. Previous studies on layout-aware scan tree synthesis only address 2-D layouts, so they cannot be directly applied to 3-D ICs. The proposed algorithm effectively optimizes both test compression rate and routing length under 3-D IC-induced constraints, and produces better results than all previous known methods.

On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the number of test sessions required to form all the rings. Previous method on ring generation algorithm uses depth-first-search (DFS) based method to generate long rings that may pass more uncovered edges. However, very few of the long rings can be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this paper, we present several techniques to generate rings that can be tested concurrently. (1) Two ring generation algorithms are proposed to generate shorter rings that can be applied in parallel to reduce overall test time. (2) Multilevel framework is applied to optimize parallelism. Experimental results show that the proposed ring generation algorithms improve test application time by 2.25X, and with multilevel framework the improvement is 4.13X. All the ring generation algorithms achieve 100% interconnect fault coverage.