Early detection of patient deterioration is crucial for reducing mortality rates. Heart rate data has shown promise in assessing patient health, and wearable devices offer a cost-effective solution for real-time monitoring. However, extracting meaningful insights from diverse heart rate data and handling missing values in wearable device data remain key challenges. To address these challenges, we propose TARL, an innovative approach that models the structural relationships of representative subsequences, known as shapelets, in heart rate time series. TARL creates a shapelet-transition knowledge graph to model shapelet dynamics in heart rate time series, indicating illness progression and potential future changes. We further introduce a transition-aware knowledge embedding to reinforce relationships among shapelets and quantify the impact of missing values, enabling the formulation of comprehensive heart rate representations. These representations capture explanatory structures and predict future heart rate trends, aiding early illness detection. We collaborate with physicians and nurses to gather ICU patient heart rate data from wearables and diagnostic metrics to assess illness severity and evaluate deterioration. Experiments on real-world ICU data demonstrate that TARL achieves both high reliability and early detection. A case study further showcases TARL's explainable detection process, highlighting its potential as an AI-driven tool to assist clinicians in recognizing early signs of patient deterioration.

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.

In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

The rapid advance of semiconductor technology exposes multifrequency designs to severe reliability loss due to incomplete at-speed testing, which is induced by ignorance of timing-related defects between clocks. However, the reduced testability caused by core-based design strategy also aggravates the difficulty in applying on-chip at-speed testing. Although previous works were able to successfully increase the quality of the at-speed testing, the diversity of on-chip clock control schemes from different components may complicate the test integration, increasing the test costs. Therefore, to accelerate the time-to-market and the time-to-volume, the development of a plug-and-play at-speed testing based on a well-defined test interface has become increasingly urgent. In this paper, a fast test integration approach for multi-clock-domain at-speed testing based on IEEE Standard 1500 is proposed. The proposed framework has been successfully integrated into an IEEE 1500-wrapped ultrawide-band design and a simple SoC design. Experiment results also confirm the feasibility of the proposed approach.

Rapid advances in semiconductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE standard 1500 are applied to test the functionality of each embedded core in system-on-chip (SoC) designs but fail to verify the corresponding timing specifications. In this paper, to achieve high quality of delay tests, hardware implementation of an embedded delay test framework including the modified test wrappers and the embedded delay test mechanism is presented to build an entirely embedded delay test environment where at-speed clock is applied inside the chip to increase test accuracy. Additionally, the proposed delay test framework is capable of supporting all current solutions of core-based delay test. The experimental results successfully demonstrate the delay testing application using the proposed framework to a crypto processor with satisfying test quality and effectiveness.