This paper explores the possibility of using visual object detection techniques for word localization in speech data. Object detection has been thoroughly studied in the contemporary literature for visual data. Noting that an audio can be interpreted as a 1-dimensional image, object localization techniques can be fundamentally useful for word localization. Building upon this idea, we propose a lightweight solution for word detection and localization. We use bounding box regression for word localization, which enables our model to detect the occurrence, offset, and duration of keywords in a given audio stream. We experiment with LibriSpeech and train a model to localize 1000 words. Compared to existing work [1], our method reduces model size by 94%, and improves the F1 score by 6.5%.

Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years. However, in recent years, the increased loss of predictability in semiconductor devices has raised concern over the ability of STA to effectively model statistical variations. This has resulted in extensive research in the so-called statistical STA (SSTA), which marks a significant departure from the traditional STA framework. In this paper, we review the recent developments in SSTA. We first discuss its underlying models and assumptions, then survey the major approaches, and close by discussing its remaining key challenges.

Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, by finding their joint probability distribution function. We consider inter-die variations, as well as intra-die variations, with correlated and random components. The correlation between power and performance arises due to their dependence on common process parameters and is shown to have a significant impact on the yield, particularly in high-frequency bins. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizing and gate-length biasing in the circuit with high efficiency and accuracy. We show how this gradient information can be effectively used by a nonlinear optimizer to perform yield optimization. The proposed yield-analysis approach is compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%. The proposed optimization approach is implemented and tested, and we demonstrate an average yield increase of 40% using gate sizing (as compared to a deterministically optimized circuit). Even higher improvements are demonstrated when both gate sizing and gate-length-biasing techniques are used.

This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling of state-of-the-art work in power reduction techniques, and also in the newly emerging area of statistical optimization applied to very large scale integration (VLSI) ICs. The lack of CAD techniques to perform multiobjective function optimization (specifically parametric yield under correlated performance metrics) is a major limitation of current CAD research. In addition, with design trends pushing towards architectures based on aggressive adaptivity and voltage scaling, CAD researchers and engineers will need to refocus efforts on enabling this type of complex design

Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This paper presents a convex-optimization-based approach to select values of supply voltages, threshold voltages, and oxide thicknesses to minimize power dissipation in a simplified abstraction of multi-Vdd/Vth/Tox CMOS designs while considering process variation. The authors use this probabilistic approach to perform optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points) and quantify the impact of rising process variations on these power-minimization techniques

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

With the increased significance of leakage power and performance variability, the yield of a design is becoming constrained both by power and performance limits, thereby significantly complicating circuit optimization. In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. We then show how this gradient information can be effectively used by a non-linear optimizer to perform yield optimization. We consider both inter-die and intra-die variations with correlated and random components. The proposed approach is implemented and tested and we demonstrate up to 40% yield improvement compared to a deterministically optimized circuit.

This paper presents a novel approach towards the simultaneous Vt-assignment and gate-sizing problem. This inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. We prove that, under our formulation, the optimal solution has discrete Vts assigned to almost every gate, thus eliminating the need for a sophisticated snapping heuristic. We show that this technique performs dual-Vt assignment and gate sizing in a very efficient manner. Compared to a sensitivity based method, we achieve average leakage savings of 31% and average total power savings of 7.4% with very efficient runtimes.

Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variability in performance and leakage of a design. While extensive work has been performed in the past on statistical analysis methods, circuit optimization is still largely performed using deterministic methods. We show in this paper that deterministic optimization quickly looses effectiveness for stringent performance and leakage constraints in designs with significant variability. We then propose a statistically aware dual-Vt and sizing algorithm where both delay constraints and sensitivity computations are performed in a statistical manner. We demonstrate that using this statistically aware optimization, leakage power can be reduced by 15-35% compared to traditional deterministic analysis. The improvements increase for strict delay constraints making statistical optimization especially important for high performance designs.

We develop an approach to minimize total power in a dual-Vdd and dual-Vth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second phase proceeds in a forward topological fashion and both sizes and re-assigns gates to high Vdd to enable significant static power savings through high Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS and dual-Vth/sizing algorithms demonstrate the advantage of the algorithm over a range of activity factors, including an average power reduction of 30% (50%) at high (nominal) primary input activities.

We present a sensitivity-based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.

Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This work presents a convex optimization based approach to select supply and threshold voltages to minimize power dissipation in generic multi-Vdd/Vth CMOS designs while considering process variation. We use this probabilistic approach to compare the optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points), and quantify the impact of rising process variations on these power minimization techniques.

We present the first in-depth study of the two existing algorithms, namely, Clustered Voltage Scaling (CVS) and Extended Clustered Voltage Scaling (ECVS), used for assigning the voltage supply to gates in integrated circuits having dual power supplies. We present a comparison of the achievable power savings using these algorithms on various benchmark circuits and first point out that ECVS does provide appreciably larger power improvements compared to CVS. We then provide a new algorithm based on ECVS that further improves the power savings by efficient assignment of the power supplies to the gates. Our new algorithm provides up to 66% power reduction and improves the power savings by up to 28% and 13% with respect to CVS and ECVS respectively. Furthermore, since level conversion is an essential component of dual power supply systems we also present the first circuit-specific sensitivity study of achievable power savings to the energy and delay penalties imposed by level conversion.

In this paper, we investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static+dynamic) in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal V/sub dd/'s and V/sub th/'s to be used in future designs. These models show the optimal second V/sub dd/ to be approximately half the nominal V/sub dd/ while the potential total power savings is significantly greater than previously anticipated (60%-65%). We describe the impact of level conversion delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements.

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.

We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1V processes. Rules of thumb are developed for optimal Vdd's and Vth's to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the total power savings is significantly greater than previously anticipated. We describe the impact of level conversion delays and highlight the tradeoff between power savings and critical path count.

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We will discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.

We describe the impact of process variation on leakage power for a 0.18mm CMOS technology. We show that variability, manifested in Ldrawn, Tox, and Nsub, can drastically affect the leakage current. We first present Monte Carlo-based simulation results for leakage current in various CMOS gates when the process parameters are varied both individually and concurrently. We then derive an analytical model to estimate the mean and standard deviation of the leakage current as a function of the process parameter distributions. We demonstrate that the results of the analytical model match well with Monte-Carlo simulations and also show the statistical mean leakage current is significantly different from the leakage predicted using a nominal case file.