Thermal hot spots and unbalanced temperatures between cores on chip can cause either degradation in performance or may have a severe impact on reliability, or both. In this paper, we propose mDTM, a proactive dynamic thermal management technique for on-chip systems. It employs multi-objective management for migrating tasks in order to both prevent the system from hitting an undesirable thermal threshold and to balance the temperatures between the cores. Our evaluation on the Intel SCC platform shows that mDTM can successfully avoid a given thermal threshold and reduce spatial thermal variation by 22%. Compared to state-of-the-art, our mDTM achieves up to 58% performance gain. Additionally, we deploy an FPGA and IR camera based setup to analyze the effectiveness of our technique.

Technology scaling in the nano-CMOS era has reached a point where coping with the failures produced by soft errors has become one of the key challenges when it comes to reliability. Akin to the fact that a register file is accessed more frequently than any other architectural component, register file protection is imperative to obstruct errors from propagating throughout a computing system. Furthermore, negative bias temperature instability (NBTI) has emerged as a major concern due to its negative impact on the lifetime of pMOS devices. Indeed, many of the pMOS transistors most affected by NBTI are in the register files as they are implemented as SRAM, which are particularly vulnerable due to their small structure size. Based on our observation that some register bits are not continuously used to represent a value stored in a register, we present a technique that exploits unused bits to improve the register file immunity against soft errors and mitigate NBTI effects. We show that our technique can reduce, on average, the register file vulnerability against multiple bit upsets by 97% (up to 100%), resulting in a high system fault coverage under various scenarios, while consuming less power and still occupying a similar area footprint compared to protecting the register file against single bit upsets (SBUs) only. The achieved result is 63% better compared to the state-of-the-art in register file protection. To compare and quantify the effect of our technique, we observe its impact on the processor's temperature using an infrared thermal camera and show that, due to consuming less power per area, our technique also operates at a lower temperature compared to protecting the register file against SBUs only. Finally, we investigate how our technique additionally moderates the stress induced by NBTI in register file SRAM cells.

Dependability has become a growing concern in the nano-CMOS era due to elevated temperatures and an increased susceptibility to temperature of the small structures. We present an overview of temperature-related effects that threaten dependability and a methodology for reducing the dependability concerns through thermal management utilizing the concept of aging budgeting.

Negative Bias Temperature Instability (NBTI) is considered one of the major reliability concerns of transistors in current and upcoming technology nodes and a main cause of their diminished lifetime. We propose a new means to mitigate the effects of NBTI on SRAM-based register files, which are particularly vulnerable due to their small structure size and are under continuous voltage stress for prolonged intervals. The conducted results from our technology simulator demonstrate the severity of NBTI effects on the SRAM cells - especially when process variation is taken into account. Based on the presented analysis, we show that NBTI stress in different registers needs to be tackled using different strategies corresponding to their access patterns. To this end, we propose to selectively increase the resilience of individual registers against NBTI. Our technique balances the gate voltage stress of the two PMOS transistors of an SRAM cell such that both are under stress for approximately the same amount of time during operation - thereby minimizing the deleterious effects of NBTI. We present mitigation implementations in both hardware and in software along with the incurred overhead. Through a wide range of applications we can show that our technique reduces the NBTI-induced reliability degradation by 35% on average. This is 22% better than current State-of-the-Art.

Accurate thermal profile estimation for FPGA, at design time, is necessary to avoid unexpected thermal hot-spots in the circuit before deploying the FPGA to the in-field operation. Both accurate dynamic and leakage power values are needed for the thermal profile estimation and they can be estimated using the FPGA vendor's tools. However these report leakage power as a single value for the whole chip, and no details are given in literature or the FPGA toolset about its distribution across the FPGA chip for the thermal simulation. To cope with this problem, we present a method for properly distributing the leakage power across the FPGA chip. The method uses a temperature-leakage loop estimation model for distributing and adapting the leakage power for more accurate thermal simulation. Furthermore, to accurately calibrate the presented method and its model and also to validate the resulting thermal profiles, we utilize an infrared thermal camera, which measures the emissions from the backside of a Virtex-5 FPGA chip. The results of testing several designs, with different sizes and frequencies, show that our approach can achieve accurate thermal-profile estimation when compared to the camera measurements, with average absolute estimation error of around 1°C across the chip.

The rapid push towards the minimization of the feature sizes of the process technology nodes in the nano-CMOS era has significantly increased the power densities and made State-of-the-Art FPGAs vulnerable to diverse problems induced by excessive temperatures. As a result, there is a prominent need to accurately study the FPGA thermal characteristics. Our experimental setup employs a thermal camera that captures the infrared emissions from the silicon wafer of an FPGA die allowing us to evaluate the accuracy of the methods conventionally used for thermal analysis, such as thermal simulations. Based on our observation that the memory interface is the thermal hotspot of an FPGA-based embedded system, we demonstrate that the cache plays a dominant thermal role by reducing memory accesses; we carefully examine the influence of various cache parameters on the FPGA temperature and propose a model linking these quantities, with an average maximum error of only 0.64°C.

Simulation is the state-of-the-art analysis technique for distributed thermal management schemes. Due to the numerous parameters involved and the distributed nature of these schemes, such non-exhaustive verification may fail to catch functional bugs in the algorithm or may report misleading performance characteristics. To overcome these limitations, we propose a methodology to perform formal verification of distributed dynamic thermal management for many-core systems. The proposed methodology is based on the SPIN model checker and the Lamport timestamps algorithm. Our methodology allows specification and verification of both functional and timing properties in a distributed many-core system. In order to illustrate the applicability and benefits of our methodology, we perform a case study on a state-of-the-art agent-based distributed thermal management scheme.

Networsk-on-chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. State-of-the-art NoC designs rely mainly on a static network configuration using fixed routing algorithms and buffer placements. These approaches are not effective in dealing with hard-to-predict system behavior, for instance due to user behavior or varying workloads, since in order for static NoCs to cover these scenarios, they would have to be designed for worst case scenarios. In this paper, we address these problems with a runtime adaptive network-on-chip (AdNoC). Focusing on the architecture-level adaptation, we present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks on-demand. Furthermore, the adaptivity requires a comprehensive, hardly intrusive, runtime observability infrastructure, i.e., using monitoring components, in order to gather data on the system state. The area overhead introduced by the adaptive scheme can be traded off against the flexibility gained. Moreover, the area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port (we achieved on an average 42% buffer saving in our experiments). We demonstrate the advantage by using various digital media applications and compare our approach to the state-of-the-art static NoC architectures e.g., Xpipe, QNoC, and Æthereal.

Reliability concerns associated with upcoming technology nodes coupled with unpredictable system scenarios resulting from increasingly complex systems require considering runtime adaptivity in all possible parts of future on-chip systems. We are presenting a novel configurable link which can change its supported bandwidth on-demand at runtime (2X-Links) for an adaptive on-chip communication architecture. We have evaluated our results using real-time multi-media and the E3S application benchmark suits. Our 2X-Links provide a higher throughput of up to 36%, with an average throughput increase of 21.3%, compared to the Normal-Full-Duplex-Links [12], [14], [17], [20] and keep performance-related guarantees with as low as 50% of the Normal-Full-Duplex-Links capacity. Our simulation shows when some links fail, the NoC with 2X-Links can recover from these faults with an average probability of 82.2% whereas these faults would be fatal for the Normal-Full-Duplex-Links.

A growing challenge in embedded system design is coping with increasing power densities resulting from packing more and more transistors onto a small die area, which in turn transform into thermal hotspots. In the current late silicon era silicon structures have become more susceptible to transient faults and aging effects resulting from these thermal hotspots. In this paper we present an agent-based power distribution approach (TAPE) which aims to balance the power consumption of a multi/many-core architecture in a pro-active manner. By further taking the system's thermal state into consideration when distributing the power throughout the chip, TAPE is able to noticeably reduce the peak temperature. In our simulation we provide a fair comparison with the state-of-the-art approaches HRTM [19] and PDTM [9] using the MiBench benchmark suite [18]. When running multiple applications simultaneously on a multi/many-core architecture, we are able to achieve an 11.23% decrease in peak temperature compared to the approach that uses no thermal management [14]. At the same time we reduce the execution time (i.e. we increase the performance of the applications) by 44.2% and reduce the energy consumption by 44.4% compared to PDTM [9]. We also show that our approach exhibits higher scalability, requiring 11.9 times less communication overhead in an architecture with 96 cores compared to the state-of-the-art approaches.

Hard-to-predict system behavior and/or reliability issues resulting from migrating to new technology nodes requires considering runtime adaptivity in future on-chip systems. Run-time observability is a prerequisite for runtime adaptivity as it is providing necessary system information gathered on-the-fly. We are presenting the first comprehensive runtime observability infrastructure for an adaptive network on chip architecture which is flexible (e.g. in choosing the routing path), hardly intrusive, and requires little additional overhead (around 0.7% of the total link bandwidth). The hardware overhead is negligible, too, and is in fact less than the hardware savings due to resource multiplexing capabilities that are achieved through runtime observability/adaptivity. As an example, our on-demand buffer assignment scheme increases the buffer utilization and decreases the overall buffer requirements by an average of 42% (the buffer area amounts to about 60% of the entire router area [19]) in our case study analysis compared to a fixed buffer assignment scheme [7]. Our runtime observability on an average also increases the connection success rate by 62% compared to the case without runtime observability for the applications from the E3S benchmark suite [6]. We show the advantages obtained through runtime observability and compare with state-of-the art communication-centric designs.

During run-time varying workloads and/or constraints in embedded systems require run-time adaptivity to provide a high degree of efficiency during any operation mode/scenario. Design time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. We are presenting the first approach of an adaptive on-chip communication scheme. It provides an adaptive routing/path allocation algorithm to meet a required level of QoS (guaranteed bandwidth). In our architecture adaptive runtime links are established by re-assigning buffer blocks ondemand. This adaptive buffer allocation scheme increases the buffer utilization and decreases the overall buffer use on an average of 42% in our case study analysis compared to a fixed buffer assignment strategy. The area overhead introduced by the adaptive scheme can be traded-off against the flexibility in order to select an available path and on-demand buffer allocation. We demonstrate the advantage by using various real world digital media applications and compare our approach to the state-ofthe- art static on-chip communication schemes.