To develop miniaturized devices for electrical impedance spectroscopy (EIS), sinusoidal signal generators (SSGs) need to be fully integrated on chip. High spectral purity and wide frequency tunability are required. In this work, a novel approach to SSG design is proposed, leveraging first-order interpolation executed entirely in the analog domain. Compared to standard SSGs based on zero-order interpolation, lower distortion is obtained for the same clock frequency. Experimental testing of a 0.18-$\mu $m CMOS prototype, employing 32 samples for interpolation, yielded average total harmonic distortion (THD) equal to 0.225% across a 100 Hz–300 kHz frequency range, with 130-$\mu $A consumption. Performance is consistent across different amplitude settings and process–voltage–temperature (PVT) conditions. Such findings potentially lay the groundwork for further analog-interpolation-based waveform generation solutions.

Thanks to their simplicity and scalability, R-2R DACs find widespread employment in present-day applications of integrated circuits, including miniaturized sensing devices and other emerging contexts. However, they typically yield limited accuracy due to mismatch errors. To tackle this issue, two dynamic element matching (DEM) techniques, customized for R-2R DACs, are herein proposed, trading off operating frequency with accuracy. Statistical behavioural simulations have been performed to compare the presented approaches, highlighting comparable performances, with reductions of the standard deviation of INL down to a factor of 0.26. Thereby, design guidelines for optimized DEM-compensated R-2R DACs are suggested.

This paper presents the experimental assessment of a recently proposed ultra-low voltage fully-differential inverter-based amplifier. Thanks to the novel common-mode stabilization loop, the amplifier reaches effective differential operations without compromising the output differential performance even at supply voltages as low as 150 mV. Experimental measurements demonstrate the amplifier functionality at supply voltages between 0.15 V and 0.5 V. In particular, a differential dc voltage gain of 22 dB, a gain-bandwidth product of 750 Hz with a capacitive load of 100 pF, and a static current consumption of only 57 nA are measured at Vdd= 0.3 V, with an area consumption of only 800 μm2.

Driven by the ongoing challenge of designing high-accuracy digital-to-analog converters (DACs) at the cost of a relatively small area occupation, optimal combination algorithms (OCAs) recently gained attention within the myriad of possible calibration techniques for DACs. OCAs show appealing properties with respect to traditional approaches such as dynamic element matching (DEM). At start-up or upon request, mismatches affecting DAC elements are measured on-chip, allowing rearrangement in the selection logic of the DAC unit elements. The newly found arrangement is, hence, used during normal operation, achieving superior linearity. As of today, several alternative OCAs have been proposed; however, designers willing to implement OCA-calibrated DACs are faced with unclear tradeoffs and insufficient design guidelines. In this work, we provide a detailed comparison of existing OCAs based on statistical behavioral simulations. Starting from this, we investigate the relationships between OCAs’ performances and circuit-level design aspects. Specifically, OCAs’ effectiveness in improving the static linearity is linked to the number of DAC bits and the accuracy of the auxiliary comparator required by every OCA. Unforeseen trends emerge, and new design considerations are suggested, fostering novel awareness on the subject of high-accuracy DAC designs enabled by OCA-based calibration techniques.