Due to their continuous nature across all the inversion regions of MOS transistors, charge-based models are a promising analytical tool for preliminary design sizing that brings the advantages of simplicity and accuracy. These models allows for the efficient exploration of a design space while reducing the computational burden associated to complete compact models. In this paper, a method to analyze the dynamic and frequency performances of a single-ended inverter-based ring oscillators is presented. The proposed analysis is based on the time-domain evaluation of the loading currents, as well as of the input and output voltages of the ring oscillator’s constituent inverters, using the Euler method. The novelty of this approach is the use of a 5-parameter charge-based model that considers short-channel effects. The proposed analysis is tested on a practical implementation in 28nm FD-SOI CMOS technology and the results, including the maximum achievable frequency and dynamic efficiency are compared to those obtained using the UTSOI2 model.

This work presents a survey based on more than 200 published papers related to sub-6 GHz wideband LNAs [1]. It investigates the trends with respect to the technology node. Moreover, it proposes a comparison between the most used topologies regarding their main performance metrics such as the gain, bandwidth, noise figure, power consumption and linearity. Based on this study, analytical predictions can be verified and appropriate architectures targeting a given set of specifications can be easily selected. The analysis highlights also the performance improvements and design trade-offs of design enhanced solutions such as noise cancelling and gm-boosting architectures.

This paper presents a simple and efficient methodology for LNA design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple but accurate 7 parameter-based model valid in all regions of operation and allows an accurate preliminary sizing based on an analytical study. The proposed model describes the main short-channel effects in advanced technologies and allows an analytical evaluation of the LNA nonlinearity. A use case using a 28 nm FD-SOI technology is proposed to reflect that the methodology is well suited for designs at weak to moderate inversion level in an advanced technology for which simulation-based studies are often used for early sizing.

Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined with a puncture-based communication method are introduced. Theoretical models of the hardware blocks are presented, outlining the impact of their specifications on the system. Moreover, we evaluate the synchronization efficiency in simulation and compare with a duty-cycled receiver topology. Improvement in power consumption of at least 26% and tight latency control are highlighted at no cost on the channel availability.

This paper presents a Pseudo-differential Ring-VCO (PRVCO) architecture optimized to improve by more than a factor of two the phase noise performance of regular single-ended inverter-based Ring-VCO (RVCO). Two RVCO topologies are compared and integrated in 28nm FD-SOI CMOS technology from STMicroelectronics. Based on a double tuning approach, each oscillator presents a Frequency Tuning Range (FTR) between 0.7 GHz and 2.8 GHz (120 % of FTR). The coarse tuning is realized by the local supply voltage variation, while the fine tuning is obtained via the transistors wide range body biasing specific to FD-SOI. Under typical configuration, the PRVCO presents a phase noise (PN) performance of - 95.7 dBc/Hz at 1 MHz offset frequency, which represents a 4 dB improvement compared to the inverter-based RVCO phase noise at 1.7 GHz. Both fabricated RVCOs performances are compared to the state-of-art regarding their oscillator's and VCO's Figure of Merit (FoM).

A 4× oversampling 18thorder digital FIR filter suitable to replace all analog baseband filters in a mobile high-data-rate wireless communication transmitter is presented. Special architecture optimizations allow an estimated output sampling rate of 10Gs/s in 65nm CMOS while respecting full spectrum mask specifications of the ECMA & IEEE standards over the radio band of 8 GHz.

Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.