Abstract This work is an attempt to address some issues related to practical hardware realization of power attack-resistant chaos-based encryption schemes. First, we introduce a new two-dimensional chaotic map based on a modified logistic-tent map. The proposed map has a very wide range of sustained chaotic and hyper-chaotic behavior over its large key parameters space. The presented map is practically realized using a digital field programmable gate array. Experimental validation of the map’s enhanced chaotic behavior is provided. Then the map is employed to efficiently generate chaotic clock signals appropriate for reliable image encryption applications. A proposed image encryption scheme which is driven by the generated chaotic clock signals is designed. The immunity against the powerful correlation power analysis attack is achieved in the proposed image encryption scheme even in the case when some secret key parameters of the encryption process are leaked. The present study paves the way to further explore how to build efficient chaos-based encryption schemes immune to other types of well-known effective attacks.

In this work, we present two new oscillator structures based on using two amplifiers surrounded by four impedances Z1−4. The structures are generic in the sense that they are not based on any specific active device and hence can be realized in numerous different ways. We focus our attention on deriving all possible canonical second-order RC and LC oscillators that can be obtained from each of the proposed structures. In some of the found circuits, the oscillation frequency can be independently tuned using one of the two amplifiers while the start-up condition is set by the other amplifier. Spice circuit simulations and experimental results are provided to validate the theory.

In this work, we show that a pinched-loop can be observed in the voltage-current plane when a series R-L circuit is current excited. Specifically, the resistance (R) in this circuit is variable and is voltage-controlled by the voltage developed across the inductor due to the exciting current. In this context, we confirm our previous results that the pinched-loop is not a characteristic of memrsitors or memrsitive systems and that it can be observed in many other nonlinear systems. Numerical simulations, circuit simulations and experimental results validate the theory.

A CMOS wideband voltage-mode fully differential all-pass filter (APF) is discussed. The APF circuit consists of three transistors, two inductors, two capacitors, and four resistors. The proposed APF employs the generic two-transistor common-source amplifier structure. Design procedures along with parasitic analysis are presented for wideband applications. The proposed APF is designed and fabricated in a 65-nm CMOS process. The operation of the proposed APF is validated by experimental and post-layout simulation results. The filter experimentally demonstrates a group delay (GD) of 59 ps at 26 GHz and it has less than 10% delay variation across a wide bandwidth of 24-29 GHz. The implemented design occupies an area of 0.09 mm2and consumes 5.1 mA from 1 V supply voltage. The noise and linearity performances of the proposed APF are validated by post-layout simulation results. The filter has a noise figure of 8.6-8.9 dB across 24-29 GHz and it achieves an input- referred IP3 of -1.14 dBm.

In this article, a synthesis methodology for analog circuit design is presented. This methodology utilizes symbolic math tools to systematically and exhaustively search for candidate analog circuits avoiding tedious manual work. The two-port network matrix representation of active devices, such as MOS transistors, paves the way for efficiently using advanced symbolic math toolboxes (e.g., in MAPLE or MATLAB) to automate the generation of new analog circuits and further investigate the effects of nonidealities and parasitics. Using this synthesis methodology new amplifiers, filters, and oscillators can be obtained starting from a predefined structure. This article aims to motivate and provide an overview of the current status of research in this area. In addition, two detailed design examples of a family of differential filters and a family of differential oscillators along with their simulations and measurement results are provided to illustrate and verify the synthesis methodology.

Fractional-order complementary filter topologies, which could be employed in various sensor applications, are presented in this paper. The core of the implementation is a fractional-order low-pass filter, while its complementary counterpart is derived through the substitution of the output of the low-pass filter with the input signal. Thanks to the utilization of current-mode signal processing, the summation operation needed for establishing the output of the complete filter is easily implemented.

Fractional-order shelving filter designs, which are used for preserving the spectral balance of the human sound perception, are introduced in this work. The main attractive offered benefit is originated from the fact that fractional-order filters offer an extra degree of freedom with regards to the slope of the stop-band attenuation, allowing an improvement in the listening experience. The implementation of the filters is performed through the utilization of the partial fraction expansion of the rational integer-order transfer functions which approximate their fractional-order counterparts. The employment of Operational Transconductance Amplifiers as active elements offers the advantage of full electronic control of the implemented filters characteristics.

In this paper, the generation of differential-input differential-output second-order active filters based on a common-source differential amplifier is systematically conducted using two-port network modeling techniques which enable exploiting the power of symbolic math CAD tools. Starting from a generic two-transistor differential-pair structure, and the maximum possible number of surrounding impedances, all possible filters are derived and classified. In particular, 35 transfer functions and a total of 876 filters are found to be possible. Due to employing a $2\times 2$ transmission matrix representation of each transistor, flexibility in examining parasitic effects on the derived transfer functions is achieved and can be easily automated within the design framework. Selected filters are constructed and experimentally verified using discrete transistors. The operation of some filters is also verified with simulations using a 65-nm CMOS process.

A simple realization of the fractional-order Mihalas-Niebur neuron model is presented in this work. The required low-pass filter is implemented using current-mirrors offering simple circuitry and, also, electronic tunability of the realized time-constant. Due to the limited bandwidth required for this application, the necessary fractional-order capacitor is realized using an appropriately configured second-order RC network. The proposed realization highlights the connection between the fractional-order and the frequency spiking of the model through appropriate simulation results, which are derived via the Analog Design Environment of Cadence software, using MOS transistor models provided by the AMS 0.35μm process.

In this paper, the generation of fully differential 2ndorder voltage-mode allpass filters is systematically studied and modeled using two-port network techniques. The proposed filters are based only on the generic two transistor common-drain differential pair and a series of surrounding RLC impedances. Five designs of possible allpass filters based on various choices of the surrounding impedances are also presented. Selected designs were verified with experimental results using discrete MOS transistors as proof of concept. One of the proposed filters was simulated in 65-nm CMOS and showed 46GHz delay-bandwidth while the delay can be electronically tuned via the bias current and independent from the pole frequency.

A new second-order MOS transistor based circuit block approximating the behavior of a fractional-order capacitor is proposed. The circuit is modular and therefore the order of the approximation can be increased by more stages of the same circuit in cascade or in parallel. Simulation results using a TSMC 65nm CMOS technology are provided and show less than 2° of phase error in two decades around the center frequency of the approximation. Experimental results of realized fractional-order capacitors and of a fractional-order relaxation oscillator are also shown.

The increasing interest in bio-impedance analysis in various fields has increased the demand for portable and low-cost impedance analyzers that can be used in the field. Simplifying the hardware is important to maintain low-cost and portability, but this is not an easy task due to the need for accurate phase and magnitude measurements. In this paper, a magnitude only hardware design is proposed and tested. The need to measure the phase is replaced by using a modified Kramers-Kronig transform to extract the phase from the magnitude information. Testing using on-shelf components, and comparisons using apple bio-impedance measurements from a professional impedance analyzer are also reported.

Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.

Fractional-order models of supercapacitors are advantageous in that they have fewer terms, offering simpler expressions to accurately describe the transient characteristics of these devices than integer-order models. When evaluating the discharge characteristics of supercapacitors, a constant current is often considered which does necessarily represent real-world applications. In this work, the voltage discharging expressions of a fractional-order model of a supercapacitor to time-varying polynomial discharging currents are presented using simulations to highlight the different cases. In addition, the parameters of a commercial supercapacitor are determined from experimental data when constant, linear, and quadratic discharging currents are assumed to highlight the implications that the current discharge waveform has on the estimated device parameters.

A fractional-order model of the B&K type 4185 commercial ear simulator is introduced in this work. It is constructed from a series connection of an integer-order inductor and a fractional-order capacitor. The proposed model is much simpler than its corresponding integer-order counterpart and can easily be implemented using Operational Transconductance Amplifiers (OTAs) and grounded capacitors in a fully resistor-less structure. The proposed realization also offers electronic tuning capability of its characteristics through the adjustment of appropriate dc currents and is realizable in fully integrated form. Evaluation of the behavior of the proposed model is performed using Cadence and the Design Kit provided by the Austrian Micro Systems 0.35μm CMOS process.

In this paper the variability of supercapacitor fractional-order model parameters are explored when extracted using a non-linear least squares optimization applied to their constant current discharging behaviour. The variability of parameters extracted 1000 different times applying the optimization process to multiple sets of simulated and experimental data are presented to validate this approach. The experimental results were collected from 4 samples of Panasonic EEC-SSR5H105 supercapacitors (1 F rating) acting as a secondary power source for an Arduino Uno system. Simulations using the average extracted parameters show less than 5% error compared to the experimental results, with all parameters from each sample also showing mean absolute deviations in the micro (10-6) range for the majority of cases.

An analog all-pass filter based transfer function synthesis method is proposed for realizing multifunctional microwave active circuits. An analog realization is obtained by replacing unit sample delays in an existing digital prototype with a second-order all-pass analog filter. A novel space time array processor (STAP) and a frequency and bandwidth agile multi-band filter have been simulated using the proposed transfer function synthesis method using measured S- parameters of a fabricated 130 nm second-order CMOS all- pass filter. Simulated array patterns of the STAP beamformer show improved side-lobe performance for better interference suppression and noise rejection. The tunability of the multi-band analog filter, in terms of the center frequency and the quality factor, is verified up to 8 GHz, which has potential applications in analog microwave front-ends.

Impedance spectroscopy is a powerful tool to study the frequency behavior of supercapacitors, but it comes with pricy hardware and postprocessing routines. Here we present a non-impedance method to extract the fractional-order model parameters (Rs, Cα, α) of a supercapacitor-assumed to be equivalent to a series association of a resistance with a constant phase element-using the magnitude response of a measurement circuit consisting of a large bandwidth operational amplifier with negative feedback. The theory behind the measurement circuit, along with the extraction method of the model parameters, and validation within 1% error using simulated and experimental results from a commercial supercapacitor are presented and discussed.

Designs of switched-current fractional-order filters are presented in this paper. The derivation of the filters is performed through a transposition of the Functional Block Diagram of the continuous-time prototype filter into discrete-time domain using the bilinear s-to-z transformation. Fully differential bilinear integrators have been employed in order to facilitate the realization of the required current inversions. The correct operation of the proposed design method has been verified through simulation in the cases of (1+a) and (3+a) order lowpass filters.

The Cole impedance model is widely used in applications involving the electrical impedance of biological tissues. Typically requiring post-processing to determine its four parameters from electrical impedance measurements. Here, a nonlinear least squares optimization routine is applied to extract the Cole impedance parameters from collected magnitude responses (not requiring direct impedance measurements). The aim is to quantify the impact of the measured frequency range, number of collected datapoints, and level of noise in the magnitude-only measurements on the accuracy of the extracted parameters. Further investigating the impact the optimization settings have on the accuracy and time required to extract the parameters. The aim is to understand these factors' effects towards the implementation of embedded systems utilizing this method to extract the impedance parameters.

Fractional-order filter realizations with Chebyshev characteristics, approximated by appropriate integer-order topologies, are realized in this work. The employed active blocks were current-mirrors and the derived filters offer the following attractive characteristics: capability of operating in a low-voltage environment, circuit simplicity and resistor-less realization. In addition, a digitally controlled current division network is employed to perform electronic adjustment of the cut-off frequency as well as the order of the filters. The performance of the proposed fractional-order filters is evaluated through the Analog Design Environment of the Cadence software and the Design Kit provided by the AMS 0.35μm CMOS process. The obtained simulation results for orders 1.2, 1.5, and 1.8 confirm that both pass-band and stop-band characteristics of the filters are preserved, while the transition from pass-band to stop-band is performed in fractional-order steps.

In this paper we propose using a non-linear least squares fitting process to estimate the impedance parameters of a fractional order model of supercapacitors from their collected step response datasets, without requiring direct measurement of the impedance or frequency response. Experimentally estimated parameters from 1 F supercapacitors verify the proposed time domain method showing less than 2% relative error between the simulated response (using the extracted fractional parameters) and the experimental step response, over the entire dataset.

In this paper we propose using a method of non-linear least squares to extract the Cole-Cole impedance parameters (Ro, R∞, α, τ) from collected frequency response datasets. We show how this method reduces the error of the extracted parameters when compared to direct extraction methods whose accuracy are limited by the measured low and high frequency gains. Parameters extracted using the non-linear least squares show up to 4 orders of magnitude lower relative error from ideal simulated datasets compared to direct methods. Experimentally extracted parameters from fruit tissue frequency responses verify the accuracy of the proposed non-linear least squares method over the direct extraction method.

In this paper we propose a fractional lowpass transfer function of the order (n + α) where n is an integer and 0α. A 1storder lowpass filter with fractional steps from 0.1 to 0.9, that is of order 1.1 to 1.9 is given as an example with its characteristics compared to 1stand 2ndorder Butterworth filters. PSPICE simulations and experimental results of a prototype filter verify the operation of the fractional step filter.

Implementing the synchronization of chaotic systems presents new challenges that are difficult to handle by using currently adopted schemes. The paper proposes an implementation of a synchronization method for a pseudo-True Random Bit Generator (PTRBG) based on chaotic systems. Synchronization of the chaotic binary sequences is achieved by using the backward iteration approach. The implementation test bed for the complete wireless communication system is based on a Chipcon wireless development kit. Assessment of the pseudo- true random bits (PTRB) generated is performed using the NIST statistical test suite.

Class-AB squaring circuits based on classical mixed four-transistor translinear cell are found to have large sensitivity with respect to the mismatches of the transistors involved in the translinear loop. In order to reduce this sensitivity, we propose the use of differentially driven mixed translinear cells. Using this cell, a voltage squaring circuit with reduced sensitivity to element mismatches is obtained. Simulation results show that the output signals of the proposed circuit exhibit very low distortion.

Chaotic oscillators capable of generating 2D scroll grid attractors are designed based on a recently proposed nonautonomous design technique. The technique relies on modifying the system equilibrium points via multiple external periodical pulse excitations. Numerical and experimental results verifying the theory are included.

We propose a novel autonomous system for chaos generation based on a third-order abstract canonical mathematical model. Nonlinearity in this system is introduced by a bipolar switching constant which reflects the behaviour of a simple inverter circuit. Two implementations of the system are given. The first uses commercially available components while the second was designed on a CMOS chip. Numerical simulations and experimental results are provided.