Demo Data from EDBT 2026 / reviewers in the wild / expert
Samrat S. Batth
dblp:90/2045
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 1 first-authorSystems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Network management and operations · 100% | |
| Theoretical computer science
1 paper |
Automata and formal languages · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Network management and operations › network testing
protocol conformance testing |
0.1 | 1 | 2008 | Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols · IEEE Trans. Computers 2008 |
Automata and formal languages › finite automata
extended finite state machines |
0.0 | 1 | 2008 | Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols · IEEE Trans. Computers 2008 |
Methods — techniques the papers use, named apart from their topics
test sequence generation · 0.2graph augmentation algorithms · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Fault masking by multiple timing faults in timed EFSM models
Yu Wang 0012, M. Ümit Uyar, Samrat S. Batth, Mariusz A. Fecko |
Comput. Networks | 3 |
| 2008 | Algorithms for Modeling a Class of Single Timing Faults in Communication ProtocolsabstractA set of graph augmentation algorithms is introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1 -clock andn-clock timing faults and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is on the same order of magnitude as that of the original specification. M. Ümit Uyar, Samrat S. Batth, Yu Wang 0012, Mariusz A. Fecko |
IEEE Trans. Computers | 2 |
| 2007 | Specification of Timed EFSM Fault Models in SDL
Samrat S. Batth, Elisangela Rodrigues Vieira, Ana R. Cavalli, M. Ümit Uyar |
FORTE | 1 |