The basic theory of t-UEC d-UED codes is developed. Methods for construction of such codes from symmetric error-correcting and asymmetric error-correcting codes are developed. Some bounds for t-EC d-UED codes are improved. Encoding/decoding procedures for these codes are discussed.>

The concept of a conditionally robust two-pattern test for testing stuck-open transistor faults in CMOS gates is introduced. Such a test is conditionally hazard-free; i.e. the transition will not produce a hazardous output provided a (partial) order is imposed on the time instants at which the components of the input pattern undergo transition. Two sources of the existence of such a partial order are identified: (1) when a set of transistors is controlled by the same logic signal, the symbolic layout (routing) information provides the knowledge of such a partial order; and (2) multipattern tests, which may be necessary to test embedded CMOS gates, can be looked upon as two-pattern tests with an imposed partial order. Algorithms are given to determine whether a two-pattern test is conditionally hazard-free under a given partial order and to compute minimal cardinality partial orders that, when imposed on a transition, make it conditionally hazard-free.>