Retrieval-Augmented Language Models boost task performance, owing to the retriever that provides external knowledge.Although crucial, the retriever primarily focuses on semantics relevance, which may not always be effective for generation.Thus, utility-based retrieval has emerged as a promising topic, prioritizing passages that provide valid benefits for downstream tasks.However, due to insufficient understanding, capturing passage utility accurately remains unexplored.This work proposes SCARLet, a framework for training utility-based retrievers in RALMs, which incorporates two key factors, multi-task generalization and inter-passage interaction.First, SCAR-Let constructs shared context on which training data for various tasks is synthesized.This mitigates semantic bias from context differences, allowing retrievers to focus on learning task-specific utility and generalize across tasks.Next, SCARLet uses a perturbation-based attribution method to estimate passage-level utility for shared context, which reflects interactions between passages and provides more accurate feedback.We evaluate our approach on ten datasets across various tasks, both indomain and out-of-domain, showing that retrievers trained by SCARLet consistently improve the overall performance of RALMs.

Traditional image-to-3D models often struggle with scenes containing multiple objects due to biases and occlusion complexities. To address this challenge, we present REPARO, a novel approach for compositional 3D asset generation from single images. REPARO employs a two-step process: first, it extracts individual objects from the scene and reconstructs their 3D meshes using off-the-shelf image-to-3D models; then, it optimizes the layout of these meshes through differentiable rendering techniques, ensuring coherent scene composition. By integrating optimal transport-based long-range appearance loss term and high-level semantic loss term in the differentiable rendering, REPARO can effectively recover the layout of 3D assets. The proposed method can significantly enhance object independence, detail accuracy, and overall scene coherence. Extensive evaluation of multi-object scenes demonstrates that our REPARO offers a comprehensive approach to address the complexities of multi-object 3D scene generation from single images.

Yilong Xu, Jinhua Gao, Xiaoming Yu, Baolong Bi, Huawei Shen, Xueqi Cheng. Proceedings of the 2025 Conference of the Nations of the Americas Chapter of the Association for Computational Linguistics: Human Language Technologies (Volume 1: Long Papers). 2025.

With many social problems nowadays, rumor detection in social media has become increasingly important. Previous works proposed classical and deep learning methods to extract information from features or rumor propagation structures. However, these methods either require lots of labeled data or are disturbed by noise nodes easily. To address these challenges, we propose a novel method that Disentangles graph representations with Contrastive learning for Rumor Detection (DCRD). Specifically, we design a graph contrastive learning strategy, significantly reducing the requirement of labeled data. We disentangle attention and redundant graph representations to extract intrinsic features and exclude the influence of redundant information. In addition, we utilize the disentangled two parts as hard negative samples to enhance contrastive learning further. Experiment results on two real-world datasets show that DCRD outperforms state-of-the-art models. More validation experiments demonstrate the data efficiency and robustness of our method.

The rapid rise of microservice architecture poses severe challenges to workflow scheduling, resource allocation, and goal optimization. However, faults and failures usually happen during workflow running. To ensure the workflow's successful execution during scheduling microservices, this article proposes a dynamic workflow scheduling algorithm by integrating cognition cost and reliability QoS for using reinforcement learning (WS-CCR). First, we explore the ‘restart policy’ of containers in the Kubernetes architecture, which lays the foundation for our work that adopts the redundancy strategy to ensure workflow operation. Then we consider the cognitive cost based on the fact that users have a cognitive process for different microservices in selecting microservices. Additionally, another optimization goal is the reliability of workflows. On this basis, we design a reasonable reward function in reinforcement learning to generate dynamic strategies. Furthermore, following some generated strategies, our engine will schedule candidate microservices for tasks to execute step by step. A series of experiments on Alibaba and business areas workflows have proven the superior performance of our algorithm. Our WS-CCR can generate better Pareto solution sets than other baselines in terms of improving the reliability of running workflows. Finally, we give a case study to prove the practicability of our method.

Workflow scheduling for microservice has become an important and challenging research topic. To design a high-performance and reliable scheduling model, we propose a dependable workflow scheduling algorithm for microservice quality of service (QoS) based on deep-Q-Network, namely the DWSM. Firstly, we utilize the redundancy strategy based on the restart strategy of the Kubernetes container to optimize the dependability of workflow. Then this paper quantifies the dependability indicator and designs the reward function based on three QoS attributes including execution time, resources consumption and dependability to generate the scheduling strategy through DQN. Finally, we utilize a real-world data set to evaluate our algorithm and compare it with several state-of-art baselines including heterogeneous earliest-finish-time (HEFT), greedy algorithm and nondominated sorting genetic algorithm (NSGA-III). Experimental results show that our DWSM algorithm achieves higher performance in dependability and saves more CPU resources. In addition to simulation, we have implemented it on a workflow engine and deployed real workflow cases to test its effectiveness in practice.

Pose-guided person image generation is to transform a source person image to a target pose. This task requires spatial manipulations of source data. However, Convolutional Neural Networks are limited by the lack of ability to spatially transform the inputs. In this paper, we propose a differentiable global-flow local-attention framework to reassemble the inputs at the feature level. Specifically, our model first calculates the global correlations between sources and targets to predict flow fields. Then, the flowed local patch pairs are extracted from the feature maps to calculate the local attention coefficients. Finally, we warp the source features using a content-aware sampling method with the obtained local attention coefficients. The results of both subjective and objective experiments demonstrate the superiority of our model. Besides, additional results in video animation and view synthesis show that our model is applicable to other tasks requiring spatial transformation. Our source code is available at https://github.com/RenYurui/Global-Flow-Local-Attention.

In order to complete design and modeling of workflow more effectively, enterprises urgently need efficient workflow recommendation technology. At present, traditional recommendation algorithms based on process structure are widely used, yet tedious modeling operations and poor recommendation accuracy are noteworthy issues. To address the above problems, based on complex workflow relationships, we utilize graph embedding in workflow recommendation to provide convenience for business process operators. In this paper, we propose a Workflow Embedding Recommendation(namely WFER) method, which can deal with the adjacency matrix of complex process to obtain more detailed feature representation, so as to calculate the similarity accurately. Therefore, we implement efficient recommendation based on workflow semantics. Moreover, this recommendation tool is suitable for both transactional workflows and scientific workflows. Finally, based on real datasets and generated datasets, we carry out experiments to compare our method with other traditional algorithms and experimental results show its effectiveness and efficiency in practice.

Image inpainting techniques have shown significant improvements by using deep neural networks recently. However, most of them may either fail to reconstruct reasonable structures or restore fine-grained textures. In order to solve this problem, in this paper, we propose a two-stage model which splits the inpainting task into two parts: structure reconstruction and texture generation. In the first stage, edge-preserved smooth images are employed to train a structure reconstructor which completes the missing structures of the inputs. In the second stage, based on the reconstructed structures, a texture generator using appearance flow is designed to yield image details. Experiments on multiple publicly available datasets show the superior performance of the proposed network.

Recent advances of image-to-image translation focus on learning the one-to-many mapping from two aspects: multi-modal translation and multi-domain translation. However, the existing methods only consider one of the two perspectives, which makes them unable to solve each other's problem. To address this issue, we propose a novel unified model, which bridges these two objectives. First, we disentangle the input images into the latent representations by an encoder-decoder architecture with a conditional adversarial training in the feature space. Then, we encourage the generator to learn multi-mappings by a random cross-domain translation. As a result, we can manipulate different parts of the latent representations to perform multi-modal and multi-domain translations simultaneously. Experiments demonstrate that our method outperforms state-of-the-art methods.

The task of event detection involves identifying and categorizing event triggers.Contextual information has been shown effective on the task.However, existing methods which utilize contextual information only process the context once.We argue that the context can be better exploited by processing the context multiple times, allowing the model to perform complex reasoning and to generate better context representation, thus improving the overall performance.Meanwhile, dynamic memory network (DMN) has demonstrated promising capability in capturing contextual information and has been applied successfully to various tasks.In light of the multi-hop mechanism of the DMN to model the context, we propose the trigger detection dynamic memory network (TD-DMN) to tackle the event detection problem.We performed a five-fold crossvalidation on the ACE-2005 dataset and experimental results show that the multi-hop mechanism does improve the performance and the proposed model achieves best F 1 score compared to the state-of-the-art methods.

Downhole electric drilling, with a motor driving the drill bit to rotate, has been an emerging trend for oil/gas drilling industry. This paper proposes an effective starting strategy for permanent magnet synchronous motors with step-up transformer, sin-wave filter and long cables for the downhole electric drilling applications. Due to the saturation effect of the transformer in low frequency region, the traditional sensorless vector control and open V/f control may fail during the startup process of the motor. The proposed starting strategy is based on a modified I-f velocity open loop control, which supplies sufficient starting torque, and the saturation effect of the transformer is effectively mitigated. A filter capacitance current compensation method is proposed to modify the inverter current references. The frequency stablization loop independent on the changeful system parameters is designed to provide stability control to mitigate speed oscillatory or motor stoppage. Finally, the feasibility and effectiveness of the proposed control strategy is verified through simulation results with Matlab/Simulink.

Extracting biomedical events from biomedical literature plays an important role in the field of biomedical text mining, and the trigger detection is a key step in biomedical event extraction. We propose a two-stage method for trigger detection, which divides trigger detection into recognition stage and classification stage, and different features are selected in each stage. In the first stage, we select the features which are more suitable for recognition, and in the second stage, the features that are more helpful to classification are adopted. Furthermore, we integrate word embeddings to represent words semantically and syntactically. On the multi-level event extraction (MLEE) corpus test dataset, our method achieves an F-score of 79.75 percent, which outperforms the state-of-the-art systems.

We propose techniques to speed up diagnostic fault simulation for circuits without full-scan which may need multi-cycle tests. First, we introduce the concept of z-sets for circuits without full scan and show how z-sets can be used in a preprocessing step to improve the performance of diagnostic fault simulation. Further, an implementation of an equivalence identification tool that executes concurrently with diagnostic fault simulation is described along with methods to increase its efficiency by prioritizing fault pair selection and reducing interprocess communication. Finally, a combination of both these techniques is analyzed and the performance benefit is presented. Experimental results on ISCAS'89 benchmarks and industrial circuits indicate that diagnostic fault simulation is substantially faster by 20.6 to 46.9% when z-sets are used along with concurrent equivalent fault identification

In this paper, we introduce two design-for-testability (DFT) techniques based on clock partitioning and clock freezing to ease the test generation process for sequential circuits. In the first DFT technique, a circuit is mapped into overlapping pipelines by selectively freezing different sets of registers so that all feedback loops are temporarily cut. An opportunistic algorithm takes advantage of the pipeline structures and detects most faults using combinational techniques. This technique is feasible to circuits with no or only a few self-loops. In the second DFT technique, we use selective clock freezing to temporarily cut only the global feedback loops. The resulting circuit, called a loopy pipe, may have any number of self-loops. We present a new clocking technique that generates clock waves to test the loopy pipe. Another opportunistic algorithm is proposed for test generation for the loopy pipe. Experimental results show that the fault coverage obtained is significantly higher and test generation time is one order of magnitude shorter for many circuits compared to conventional sequential circuit test generators. The DFT techniques do not introduce any delay penalty into the data path, have small area overhead, allow for at-speed application of tests, and have low power consumption.

Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.

We present a new clock-control DFT technique for sequential circuits, based on clock partitioning and selective clock freezing, and we use it to break the global feedback loops and to generate clock waves to test the resulting sequential circuit with self-loops. Clock waves allow us to significantly reduce the complexity of sequential ATPG. Unlike scan, our non-intrusive DFT technique does not introduce any delay penalty; the generated tests may be applied at speed, have shorter application time, and dissipate less power.

In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.

We present a new approach to built-in self-test (BIST) for logic circuits that achieves comparable fault coverages to scan BIST with less hardware overhead and no impact on performance. We combine clock partitioning to create independent clocks with a selective freezing of clock signals to form various pipeline configurations during testing. Since no scan operations are performed, tests can be applied at the operational speed of the circuit. Experimental results are presented for several benchmark circuits to demonstrate the effectiveness of the approach.

Efficient diagnosis of faults in VLSI circuits requires high quality diagnostic test sets. In this work novel techniques for diagnostic test generation are proposed that require significantly less time than previous methods. The set of fault pairs left undistinguished by a detection-oriented test set is first filtered to target only testable faults. Then diagnostic test generation is performed using a genetic algorithm (GA) combined with a diagnostic fault simulator. A new fitness metric is proposed for the GA that accurately measures the quality of candidate sequences while requiring a limited amount of CPU time. Experimental results illustrate the effectiveness of the approach for sequential circuits.

Correct operation of logic circuits requires not only the functional correctness, but also the correctness of temporal behavior. This paper deals with the problem of delay testability of two-level circuits through adding extra inputs. A design of delay-verifiable combinational logic by adding extra inputs is proposed, and a synthesis procedure is given. Experimental results show that the hardware overhead is about 1/3 of that of the methods proposed previously (1987, 1991), which aim at robust testable or VNR testable circuits. In fact, it is good enough to guarantee delay verifiability to satisfy the requirement of temporal correctness.