This paper investigates the implementation of high radix addition based on the electron counting logic design style in single electron tunneling (SET) technology. A previous proposal for such an adder assumed the presence of a conditional charge movement (MCke) block which was only described as a black box. First, this paper proposes two possible MCke block implementations, each of which is described in detail and validated by means of simulation. Second, one of the proposed MCke implementations is utilized in the design of a 6-bit radix-8 adder. The resulting adder circuit is verified by simulation and evaluation indicated that it requires 187 circuit elements, has a delay of 4.15 ns (assuming an error probability P/sub error/ and a consumed energy of 224 meV).

This work investigates the single electron tunneling (SET) technology-based computation of basic addition related arithmetic functions, e.g., addition and multiplication, via a novel computation paradigm, which we refer to as electron counting arithmetic, that is based on controlling the transport of discrete quantities of electrons within the SET circuit. First, assuming that the number of controllable electrons within the system is unrestricted, we prove that the addition of two n-bit operands can be computed with a depth-2 network composed out of 3n+1 circuit elements and that the multiplication of two n-bit operands can be computed with a depth-3 network composed out of 4n-1 circuit elements. Second, assuming that the number of controllable electrons cannot be higher than a given constant r determined by practical limitations, we prove that the addition of two n-bit operands can be computed with a depth-(n/r+3) network composed out of 3n+1+n/r circuit elements. Under the same restriction, we suggest methods to reduce the addition network depth in the order of logn/r and to perform n-bit multiplication in an O(logn/r) delay. Finally, we propose SET-based implementations for a set of basic electron counting building blocks and implement a number of circuits operating under the electron counting paradigm as follows: 4-bit digital to analog converter, 5-bit analog to digital converter, 4-bit adder, and 3-bit multiplier. All proposed implementations are verified by means of simulation.

We investigate the implementation of basic arithmetic functions, such as addition and multiplication, in single electron tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: n-bit addition can be implemented with a depth-2 network built with O(n) circuit elements; n-input parity can be computed with a depth-2 network constructed with O(n) circuit elements and the same applies for n/logn counters; multiple operand addition of m n-bit operands can be implemented with a depth-2 network using O(mn) circuit elements; and finally n-bit multiplication can be implemented with a depth-3 network built with O(n) circuit elements.