Over the past few years, several research groups have introduced innovative hardware designs for Trusted Execution Environments (TEEs), aiming to secure applications against potentially compromised privileged software, including the kernel [ 10 , 63 ]. Since 2015 [ 94 ], a new class of software-enabled hardware attacks leveraging energy management mechanisms has emerged. These internal energy-based attacks comprise fault [ 86 ], side-channel [ 46 ], and covert channel attacks [ 28 ]. Their aim is to bypass TEE security guarantees and expose sensitive information such as cryptographic keys. They have increased in prevalence in the past few years [ 9 , 24 , 40 ]. Popular TEE implementations, such as ARM TrustZone and Intel SGX, incorporate countermeasures against these attacks. However, these countermeasures either hinder the capabilities of the power management mechanisms or have been shown to provide insufficient system protection [ 9 , 55 ]. This article presents the first comprehensive knowledge survey of these attacks, along with an evaluation of literature countermeasures. We believe that this study will spur further community efforts toward this increasingly important type of attacks.

With the escalating concern about global warming, the environmental impact of electronic devices must be scru-tinized. Life Cycle Assessments (LCA) reveal that Integrated Circuits (ICs) are the primary contributors to greenhouse gas emissions in these devices. However, performing an inventory to determine the ICs impact is a complex task due to missing data and the existing studies on ICs have been neglecting CMOS Image Sensors (CIS). Despite the surge in CIS usage, particularly in smartphones, there is a lack of comprehensive models to assess their en-vironmental impact. This paper proposes a multi-level set of models that leverage available information while considering the specificities of CIS. The most comprehensive model incorporates factors such as the total silicon area, geographical location (influencing the energy mix), and the technology node. To accommodate scenarios with incomplete data, subsequent models are designed to effectively utilize averaged parameters. The proposed models are applied to sensors manufactured by STMicroelectronics and Sony, and the results are compared with existing LCA results from Fairphone. Our approach provides a more comprehensive understanding of the environmental impact of CIS, contributing to the broader goal of reducing the carbon footprint of electronic devices. Our results suggest that the carbon impact of a Fairphone 4 image sensor is likely higher than previously estimated, with a significant gap between our findings and the expected value.

The Internet of Things (IoT) has succeeded to be one of the important future communication technologies. The evolution of IoT has accelerated along with the emergence of 5G considered as a leading IoT service provider. In this context, the low power wide area network (LPWAN) has recently attracted attention as it provides an impeccable infrastructure for massive Machine-Type Communications (mMTCs). Long range wide area network (LoRaWAN) is one of the most adopted LPWAN technologies in the world. However, an efficient integration of LoRaWAN technology into the 5G system (5GS) is required. In this article, we review briefly related work trying to integrate LoRaWAN into the 5GS. Then, we present our solution for the integration and we detail the adopted network architecture. We propose new authentication methods based on the extensible authentication protocol (EAP) providing secure access, and an adaptation function to attain seamless and efficient integration. In addition, we evaluate our solution in terms of performance and security. Moreover, a comparison of our solution with related work confirms the efficiency of our solution.

Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modeling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this article is, first, to provide an overview of the register transfer level to transistor level power modeling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works.

In this article, we consider the mobility of an end device (ED) in low-power wide-area networks (LPWANs) and we focus on the continuity of the ED session with the application server when this ED is moving from the coverage of one operator to that of another one. One of the methods to achieve the continuity of the session after roaming is the use of an IPv6-based scheme. As LPWAN is characterized by a fixed message rate and very small bandwidth as well as asymmetric communication, an efficient header compression scheme is required. Recently, the Internet Engineering Task Force LPWAN working group has proposed a static context header compression (SCHC) to compress IPv6 into LPWAN through a rule-based mechanism. In this article, we first extend the SCHC scheme to support session continuity and the new scheme is called mobile SCHC (MSCHC). MSCHC consists of several contexts, instead of the static context for SCHC and we also improve the use of the memory by dividing the rules into layers. Then, we investigate the mobility of the ED to show how the continuity of the session can be achieved while transmitting and receiving data when the ED is roaming between different operators. The proposed solution is based on the use of light mobile IPv6 messages compressed with MSCHC. Finally, the proposed mechanism is implemented in the popular LoRaWAN technology, evaluated and compared with the existing solutions provided by the LoRaWAN v1.1 standard.

In this article, we present a new, simple, accurate, and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dynamic power consumption, which is application-, technology-, frequency-, and data-stimuli dependent. To model the power and the behavior of digital components, we adopt the Artificial Neural Networks (ANNs), while the final target technology is Application Specific Integrated Circuit (ASIC). The main characteristic of the proposed method, called NeuPow, is that it relies on propagating the signals throughout connected ANN models to predict the power consumption of a composite system. Besides a baseline version of the NeuPow methodology that works for a given predefined operating frequency, we also derive an upgraded version that is frequency-aware, where the same operating frequency is taken as additional input by the ANN models. To prove the effectiveness of the proposed methodology, we perform different assessments at different levels. Moreover, technology and scalability studies have been conducted, proving the NeuPow robustness in terms of these design parameters. Results show a very good estimation accuracy with less than 9% of relative error independently from the technology and the size/layers of the design. NeuPow is also delivering a speed-up factor of about 84× with respect to the classical power estimation flow.

In this paper, we present a flexible, simple and accurate power modeling technique that can be used to estimate the power consumption of modern technology devices. We exploit Artificial Neural Networks for power and behavioral estimation in Application Specific Integrated Circuits. Our method, called NeuPow, relies on propagating the predictors between the connected neural models to estimate the dynamic power consumption of the individual components. As a first proof of concept, to study the effectiveness of NeuPow, we run both component level and system level tests on the Open GPDK 45 nm technology from Cadence, achieving errors below 1.5% and 9% respectively for component and system level. In addition, NeuPow demonstrated a speed up factor of 2490X.

Today reducing power consumption is a major concern especially when it concerns small embedded devices. Power optimization is required all along the design flow but particularly in the first steps where it has the strongest impact. In this work, we propose new power models based on neural networks that predict the power consumed by digital operators implemented on Field Programmable Gate Arrays (FPGAs). These operators are interconnected and the statistical information of data patterns are propagated among them. The obtained results make an overall power estimation of a specific design possible. A comparison is performed to evaluate the accuracy of our power models against the estimations provided by the Xilinx Power Analyzer (XPA) tool. Our approach is verified at system-level where different processing systems are implemented. A mean absolute percentage error which is less than 8% is shown versus the Xilinx classic flow dedicated to power estimation.

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. This is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. This approach has been evaluated in a use-case application. The preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

In the last decade, the research on CPU-FPGA hybrid architectures has become a hot topic. One of the main challenges in this domain consists in efficiently and safely managing dynamic partial reconfiguration (DPR) resources. This paper focuses on the management of the reconfiguration by an hypervisor on an ARM-FPGA platform. Using the virtualization approach, virtual machines (VM) may access resources independently, being unaware of the existence of other VMs. The purpose of our work is to provide an abstract and transparent interface for virtual machines to access reconfigurable resources. The underlying infrastructure of partial reconfiguration management is hidden from the virtual machines, so that software developers do not need to consider the implementation details. We propose a framework where DPR accelerators are presented as virtual devices, which are universally mapped in each VM space as ordinary peripherals. The hypervisor automatically detects VM's requests for DPR resources and handles them dynamically according to a preemptive allocation mechanism. Our custom hypervisor guarantees the independent and isolation of VM domains. We also evaluate the efficiency of our framework by measuring the critical overheads during DPR management and allocations. The results demonstrate that our mechanism is implemented with low overhead.

This paper deals with the implementation of a new reconfigurable architecture for the computation of Fast Fourier Transform (FFT) in the context of digital terrestrial television broadcasting (DTTB). The proposed architecture allows more possibilities in the choice of the FFT size. In this paper, two algorithms (Radix algorithm and Winograd Fourier Transform Algorithm (WFTA)) are presented. These may be used to compute a FFT of size 2048 (2K), 4096 (4K), 8192 (8K) or 3780 that are utilized in three of the most important DTTB standards. The reconfigurable architecture is presented. The time performances and resources requirement are provided in comparison with classical architectures.

High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA accelerator, Hamburg, Germany, followed by a section on the importance of hardware preprocessing for such systems, and finally some new architectural ideas for using field programmable gate arrays in very high-speed neural-network triggers at upcoming experiments.