Hardware Trojans (HTs) are regarded as a security threat in the information society. HTs are unintentionally injected into LSI circuits by untrusted entities before the chip fabrication. HTs trigger malicious operations such as information leakage without designers noticing their operations. This paper proposes fine-grained power domain partitioning, which is a circuit design technique for detecting HT activities. This paper assumes a scenario where a fab injects HTs into the taped-out layout data and that circuit designers test the presence of HTs by using side-channel information (power consumption) of fabricated chips. Fine-grained power domain partitioning decomposes the power domain of target circuit into multiple power domains, enabling to effectively measure the small power consumption introduced by activities of tiny HTs. The measurement result using an HT-injected Advanced Encryption Standard (AES) circuit with fine-grained power domain partitioning shows that HTs can be detected.

To enhance the scalability of quantum computers, CMOS circuits operating at cryogenic temperatures (Cryo-CMOS) are being extensively studied for qubit control applications. Designing robust Cryo-CMOS integrated circuits necessitates a transistor model applicable at cryogenic temperatures. Recently, a sparse Gaussian process (SGP)-based modeling method was introduced to consistently model the current characteristics across the room to cryogenic temperatures. However, this method is limited to modeling the current characteristics alone and does not address behaviors in the subthreshold region. In this paper, we extend the SGP-based approach to accurately represent ultra-steep subthreshold slopes at cryogenic temperatures and integrate it into the BSIM-BULK model for the comprehensive representation of transistor behavior. Evaluations using transistors fabricated with 22 nm technology demonstrate that the proposed model effectively simulates the transitions between off-current and on-current at 4 K and that our model can be applicable to predict the DC and transient characteristics of an inverter.

This paper extends the low-temperature modeling capabilities of an industry-standard compact metal-oxide-semiconductor field-effect transistor (MOSFET) model by incorporating physics-based representations of cryogenic effects in semiconductors. Specifically, the incomplete dopant ionization effect is integrated into the bulk Fermi potential calculation of the compact model and applied as a threshold voltage shift in the formulation of Poisson's equation. Temperature-related models for bandgap energy, saturation velocity, and contact resistance at the source/drain regions are also enhanced. Using transistors fabricated with 22 nm process technology, we demonstrate that this consistent modeling approach accurately reproduces current-voltage and threshold voltage-temperature characteristics across a temperature range from 300 K to 4 K.

It is well-known that operating transistors in low-temperature environments improves their characteristics. This has led to the expansion of integrated circuit (IC) applications at low temperatures, including high-performance computers and controllers for quantum computers. On the other hand, hardware Trojans (HTs) pose a severe concern, threatening the authenticity of ICs. This study proposes a new HT circuit, referred to as Cryo-HT, that can be activated by the increased discharge time of a metal-oxide-semiconductor (MOS) capacitor at low temperatures. We fabricated an advanced encryption standard (AES) circuit with Cryo-HT using 180 nm process technology. We demonstrate that Cryo-HT is not activated at room temperature but activates at 213 K to reveal the AES encryption key.

Hyperdimensional computing (HDC) can efficiently perform various cognitive tasks efficiently by mapping data to hyperdimensional vectors with thousands to tens of thousands of dimensions. However, the primary operations of HDC—Bind, Permutation, and Bound—need to be executed more efficiently on a standard CPU platform. This study introduces a novel computational platform, EcoFlex-HDP, specifically designed for HDC. EcoFlex-HDP exploits the parallelism and high memory access efficiency of HDC operations to achieve low computation time and energy consumption, outperforming the CPU. Furthermore, it can work cooperatively with a CPU, enabling integration with existing software, providing flexibility to apply new algorithms, and contributing to the development of an HDC ecosystem. Through experimental evaluations with a Cortex-A9 processor, HDC operations were shown to be accelerated by a maximum of 169 times. Furthermore, EcoFlex-HDP was confirmed to improve the energy-delay product by up to 13,469 times when training an image recognition task. All source codes for our platform and experiments are available at https://github.com/yuya-isaka/EcoFlex-HDP.

Research on dedicated circuits for multiply and accumulate processing, which is vital to machine learning (ML), using memristors has attracted considerable attention. However, memristors have unknown operating principles, making it challenging to create compact models with sufficient accuracy. This study proposes a compact modeling method based on Gaussian process for memristors. Although various ML-based modeling methods have been proposed, only the reproduction accuracy has been evaluated using SPICE circuit simulator, and long learning times have not been sufficiently discussed. The proposed method reduces the learning and inference times using a Gaussian process with considering sparsity. An evaluation using data from memristor devices obtained by actual measurements demonstrates that the proposed method achieves over 2,629 times faster than conventional method using long short-term memory (LSTM). Moreover, inference on a commercial SPICE simulator can be performed with the same accuracy and computation time. All experimental environments, including the source code, are available at https://github.com/sntnmchr/SGPR-memristor/blob/main/README.md.

Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale integrated circuit (LSI) testing while maintaining the test quality. In this method, the performance of unmeasured LSI circuits manufactured on a wafer is statistically predicted from a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in wafer. However, actual wafers may have discontinuous variations that are systematically caused by the manufacturing environments, such as shot dependence. In this study, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into the systematic discontinuous and global components to improve the estimation accuracy. An evaluation performed using an industrial production test dataset shows that the proposed method reduces the estimation error for an entire wafer by over 33% compared to conventional methods.

Machine-learning-based test escape detection is gaining attention as a novel approach for detecting faulty large-scale integrated circuits (LSIs) that traditional methods fail to detect. In such scenarios, a model is developed by learning a significant amount of data from the LSI test results and used to test the manufactured LSIs. However, because manufactured LSIs are subject to lot management, the data used for learning are transmitted sequentially, necessitating restarting the learning process from the beginning at each manufacturing stage when new data arrive, leading to prolonged learning times. In this study, we propose a novel test escape detection method utilizing a transfer learning technique that reduces learning times while preserving test accuracy by learning the data of newly manufactured LSIs while maintaining the previously learned model. Evaluations utilizing the LSI production test data indicated that the proposed method can decrease the learning time by more than 40.40% without compromising the test accuracy.

Although automotive semiconductors must comply with the standard dynamic part average testing (DPAT) defined by the Automotive Electronics Council, it remains challenging to detect outliers that deviate from the spatial trend within a wafer. Outlier detection using Gaussian process (GP) regression has recently been proposed and outperformed DPAT. However, the detection performance degrades when faulty large-scale integrations are densely included in the regression. Furthermore, the applicable test items are limited because of the long computation time for regression. We propose an outlier detection method by applying ensemble learning to GP regression for simultaneously improving the detection performance and shortening the learning time. Experimental results on industrial production test data demonstrate that the proposed method improves the robustness against latent faulty chip detection by 15.6% while reducing the computation time by 98.6% compared with the conventional GP-based method.

In this paper, we propose a novel method for predicting the characteristic failure rate from a small amount of data with high accuracy using the posterior distribution of the Gaussian process. In the proposed method, using multiple lots, a local pattern on the wafers is estimated from the measurement results of the target-probe test item for failure-rate prediction. For failure-rate prediction, the global trend of each wafer is predicted by the Gaussian process using WAT data and superimposed on the local pattern. The proposed method derives the failure rate of each die based on the posterior distribution using the Gaussian process in the global trend calculation. Experiments using industrial semiconductor manufacturing data demonstrate that the proposed method can reduce the estimation error by approximately 70% compared to a conventional method.

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates$1.78\times $better mitigation for multiple input duty cycles compared to the conventional method.

The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.

With the expansion of the semiconductor supply chain, recycled field-programmable gate arrays (FPGAs) have become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the presence of known fresh FPGAs (KFFs) as the training data used for machine-learning-based classification, which is an impractical assumption. In this study, we propose a novel KFF-free recycled FPGA detection method based on an unsupervised anomaly detection scheme. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes two recycled FPGAs from 10 fresh FPGAs. In contrast, a conventional KFF-free recycled FPGA detection method results in certain misclassification.

This research work presents a novel method for the detection of recycled field-programmable gate arrays (FPGAs). In this method, delay information of all paths in look-up tables (LUTs) of configurable logic blocks in the FPGAs is analyzed exhaustively by employing an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path of all LUTs in the FPGA, it considerably increases the RO measurement cost. Furthermore, X-FP yields a large amount of measurement data causing the "curse of dimensionality" problem when used as a feature vector in the machine learning (ML) based detection system. To combat these challenges while applying the X-FP characterization, we additionally propose two techniques for realizing accurate and efficient recycled FPGA detection: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement. The WID modeling properly reflects the process variation of each FPGA, and model parameters extracted by the modeling are utilized as a feature vector in the ML-based detection to classify target FPGAs as either fresh or aged. Through experiments using commercial FPGAs, we demonstrate that the proposed method combining the VP and WID modeling on the X-FP characterization achieves high-accuracy recycled FPGA detection at a low measurement cost.

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.

In this study, a novel method for the detection of recycled field-programmable gate arrays (FPGAs) is proposed. This method is based on with-in die (WID) process variation model over an exhaustive path characterization [referred to as exhaustive-fingerprint (X-FP)]. In the proposed method, X-FP is capable of fully characterizing frequencies on all paths in look-up tables (LUTs) using advanced ring oscillator (RO) design to exhaustively capture deterioration by aging. Although machine learning (ML)-based classification is often used for recycled FPGA detection, X-FP yields a large amount of measurement data, which cannot be appropriately handled by typical ML algorithms, if they are used as a feature vector. The proposed method utilizes the model parameters extracted by WID variation modeling as the feature vector in the ML algorithm. These model parameters simply and accurately represent the process variation for each FPGA. In this way, the ML-based fresh/recycled classification works very well with the simple feature vector. Experiments using 50 commercially available FPGAs reveal that X-FP can capture the degradation effects, which cannot be detected by conventional methods. Moreover, the WID modeling achieves 99.6% feature size reduction per one FPGA. It also demonstrates that the model parameters exhibit good distance properties between fresh and aged FPGAs. Additionally, the ML-based classification which uses a one-class support vector machine can successfully detect 2 aged FPGAs (48 h accelerated aging) without any misclassification and another 4 aged FPGAs (24 h accelerated aging) with a very few misclassifications as fresh FPGAs.

In this paper, impact of device parameter variation on current sharing between silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in parallel has been studied via Monte Carlo simulation. Paralleled MOSFETs driving an inductive load in a switching circuit, which are expressed by using a surface-potential-based SiC MOSFET model, have been analyzed. From the simulation results, dominant device parameters that affect the mismatch in the SiC MOSFET currents are identified. We also evaluate the effect of current mismatch on the energy loss imbalance. In our analysis, the model parameters related to flat-band voltage, channel length modulation, and current gain factor are found to be particularly important.

Device identification using challenge-response pairs (CRPs), in which the response is obtained from a physically unclonable function (PUF), is a promising countermeasure for the counterfeit of integrated circuits (ICs). To achieve secure device identification, a large number of CRPs are collected by the manufacturers, thereby increasing the measurement costs. This paper proposes a novel scheme, which employs a logic built-in self-test (LBIST) circuit, to efficiently collect the CRPs during production tests. As a result, no additional measurement is required for the CRP collection. In addition, the proposed technique can counter machine-learning (ML) attacks because of the complicated relationship between challenge and response through the LBIST circuit. Through the proof-of-concept implementation, in which a field-programmable gate array (FPGA) is used, we demonstrate the PUF performance can be evaluated by a test pattern generated by the LBIST circuit. Furthermore, the vulnerability due to ML attacks using a support vector machine (SVM) and random forest (RF) is lowered by more than two times compared to the naive usage of PUF.

While silicon carbide (SiC) MOSFETs can tolerate high-voltage and high-temperature operations with low power loss, long-term reliability of SiC devices is of a concern due to the threshold voltage shift caused by bias temperature instability (BTI). Although the industry-standard BTI characterization method can measure long-term threshold voltage fluctuation, it is hard to quantify the fluctuation under the actual switching operation. In this paper, we propose a long-term BTI characterization method that reflects a realistic switching operation of power devices. We demonstrate the effectiveness of the proposed method using a commercial SiC MOSFET and then discuss the suitable model to represent BTI on the basis of the measurement data.

We propose a novel recycled field programmable gate array (FPGA) detection method based on with-in die (WID) variation modeling. Model parameters extracted by the WID modeling simply but accurately represent the process variation of each FPGA, and thus, by using the model parameters as feature vector, machine learning effectively classifies target FPGAs into fresh or aged. Through experiment on commercial circuit simulator, the proposed method achieves 99.6% feature vector size reduction per FPGA with showing 96.0% detection accuracy; while our silicon result using commercial FPGA demonstrates the model parameters have a good distance properties between fresh and aged.

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads, and thus path delay degradation is strongly dependent on each use case. In this paper, we propose a subset simulation (SS) framework that efficiently and accurately finds the worst case workload and the failure probability covering various workloads. In the proposed method, workloads that yield worst aged delay are efficiently generated by the NBTI-aware Markov chain Monte Carlo method. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to the naive Monte Carlo method. From the result of the SS, feasible workload that gives worst aged delay is obtained.

Resistive random access memory (ReRAM) has several attractive features such as high-storage-density and high-switching with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance than that of dynamic random access memory (DRAM) or static random access memory (SRAM). Hence, error correction code (ECC) circuit is indispensable for realizing reliable ReRAM storage. For this purpose, in this paper, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with highly frequent write operations are implemented by the conventional CMOS technology and the others are implemented by the memristors to keep a balance between the area overhead and reliablity. Through numerical experiments, we demonstrate that the proposed ECC circuits have less area and high reliability compared to ECC circuits that are fully implemented by memristors, and achieves less area while preserving the reliability compare to ECC circuits that are fully implemented by CMOS technology, where an area reduction of 19.9% is achieved for data words with 1,024 bits and the area reduction is improved as the data bit length increases.

A hardware Trojan (HT) denotes the malicious addition or modification of circuit elements. The purpose of this work is to improve the HT detection sensitivity in ICs using power side-channel analysis. This paper presents three detection techniques in power based side-channel analysis by increasing Trojan-to-circuit power consumption and reducing the variation effect in the detection threshold. Incorporating the three proposed methods has demonstrated that a realistic fine-grain circuit partitioning and an improved pattern set to increase HT activation chances can magnify Trojan detectability.

In test of large scale integration (LSI) circuit, test escape is always regarded as a critical issue since significant cost is imposed to manufacturing cost. In this paper, we propose a novel outlier screening method for test escape. The proposed method exploits variational autoencoder (VAE) that is widely used to design complex generative model in artificial neural network field. While a typical autoencoder (AE) simply extracts features of training data, the VAE does it as probability distribution, and thus it can avoid potential risk of overfitting by using the probability distributions as a regularizer. Moreover, the proposed method effectively detects test escapes by utilizing the probability distributions as likelihood function of good chips. Through experiments using an industrial production test data, we demonstrate that the proposed method detects test escapes more than approximately 8.5 times as compared to that using a conventional AE-based method.

The relentless technology scaling calls for reduced supply voltage for dynamic power suppression. On the other hand, transistor threshold voltage cannot be scaled at the same pace to avoid excessive leakage power. Consequently, the noise margin is significantly reduced, leading to the deployment of various noise management systems that handle runtime voltage emergencies. Most of these systems rely on on-chip noise sensors, which are large in size and consume significant power. To tackle this issue, in this paper we propose a sensor-less voltage emergency estimation framework. It explores the relationship between switching activities and noise, and takes advantage of block sparse compressed sensing developed by the signal processing society. Experimental results on a few industrial designs show that by monitoring registers, voltage emergencies can be successfully predicted.

High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through side channel analysis. In this work, we present an efficient Trojan detection approach in the presence of elevated process variations. The detection sensitivity is sharpened by 1) comparing power levels from neighboring regions within the same chip so that the two measured values exhibit a common trend in terms of process variation, and 2) generating test patterns that toggle each cell multiple times to increase Trojan activation probability. Detection sensitivity is analyzed and its effectiveness demonstrated by means of RPD (relative power difference). We evaluate our approach on ISCAS'89 and ITC'99 benchmarks and the AES-128 circuit for both combinational and sequential type Trojans. High detection sensitivity is demonstrated by analysis on RPD under a variety of process variation levels and experiments for Trojan inserted circuits.

As the transistor process technology continues to scale, the aging effect posits new challenges to the already complex static timing analysis (STA) process. In this paper, we first observe that aging can be thought of a type of correlated dynamic on-chip variations (OCV), and identify the problem introduced by such type of OCV. In particular, we take the negative bias temperature instability (NBTI) as an example dynamic OCV mechanism. We then propose a learning-based STA (LSTA) library to "predict" the timing of gates by capturing the correlation between our designed predictors. In the experiment, we used a linear regressor, support vector regression, and a non-linear method, random forest, to create the prediction model. An ISCAS'89 benchmark circuit is used as a training sample to for the algorithms to learn the aging model of gates, and the accuracies of the model is then tested on two processor-scale designs using the library are evaluated, achieving a maximum absolute error of 3.42%.

Negative bias temperature instability (NBTI) has become one of the major reliability concerns for nanoscale CMOS technology. The NBTI effect degrades pMOS transistors by stressing them with negatively biased voltage, while the transistors heal themselves as the negative bias is removed. In this paper, we propose a cross-layer mitigation technique for NBTI-induced timing degradation in processors. The NOP (No Operation) instruction is replaced by a custom NOP instruction for healing purpose. Cells that are likely to be stressed under negative bias are classified and their upstream cell will be replaced by the internal node control (INC) logics. Upon encountering a custom NOP instruction, the INC logics will force the NBTI-stressed cell to be in its healing mode. The optimal INC logic insertion through genetic programming approach achieves much greater delay mitigation of 44.3% than prior works in a 10-year span with less than 4% of power and negligible area overhead.

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300x reduction in the sheer number of paths.

Post-fabrication performance compensation and adaptive delay testing are indispensable means for improving yield and reliability of LSIs, The global parameter estimations, such as of threshold voltages, play a key role in maximizing their effectiveness. This paper proposes a novel technique that realizes an accurate device-parameter estimation through Fmaxtesting framework. In the proposed method, statistical path delay distributions of sensitized paths in Fmaxtesting are utilized to calculate device-parameters, such that they most likely explain the measurements in the Fmaxtesting. Two estimation procedures are proposed: one utilizes discrete Bayesian estimation and the other uses maximum likelihood estimation. Numerical experiments demonstrate that both methods achieve 2.5mV accuracy in estimating threshold voltages.

In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal set of test patterns for each chip, and thus the test coverage is improved and the test time is reduced. The test pattern is chosen on the basis of parameter estimations measured using an on-chip sensor with respect to statistical timing information. We also propose a novel metric to quantize the test coverage suitable for evaluating the test quality of parametric faults. Our experimental results using an industrial design show that the proposed flow significantly improves the parametric fault coverage and test efficiency compared to conventional test flows.

Application of IDDQ testing to LSIs fabricated using advanced process technology is becoming increasingly difficult due to large variability of scaled devices. In this paper, we propose a novel technique that adaptively determines per-chip current-threshold for IDDQ testing to enhance test accuracy. In the proposed technique, process condition of a chip and fault-sensitization vector are first estimated based on measured IDDQ currents through Bayesian inference. Then, using the estimated process condition, a statistical distribution of the leakage current for each test pattern is calculated and suitable current-threshold is determined by the distribution. Simulation experiments demonstrate that the proposed technique can successfully detect a very small leakage fault, down to 16% of the nominal IDDQ current with the test escape ratio of 3.1 %.

Post-fabrication performance compensation and adaptive delay testing are effective means to improve yield and reliability of LSIs. In these methods, process parameter estimation plays a key role. In this paper, we propose a novel technique for accurate on-chip process parameter estimation. The proposed technique is based on Bayes' theorem, in which on-chip parameters, such as threshold voltages, are estimated by current signatures obtained within a regular IDDQ testing. No additional circuit and additional measurements are required for the purpose of estimation. Numerical experiments demonstrate that the proposed technique can achieve less than 10 mV accuracy in estimating threshold voltages.

A novel technique that estimates on-chip process parameters, such as threshold voltages or channel length, is proposed. The proposed method is particularly useful as process condition estimator for reliability and yield enhancement techniques such as adaptive delay test or post-fabric performance compensation. Test paths consisting of a flip-flop and designated delay circuit, which is sensitive to individual process parameters, are inserted to obtain simultaneous delay inequalities. Then, the inequalities are solved for process parameters. The test path insertion is only on short paths to reduce delay and area overhead. Through numerical experiments, the proposed estimation flow using 150 paths achieve 10mV accuracy in estimating threshold voltages.

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

Test compression / decompression method using variable length coding is an efficient method for reducing the test application cost, i.e., test application time and the size of the storage of an LSI tester. However, some coding imposes slow test application, and consequently it requires large test application time in spite of its high compression. In this paper, we clarify the fact that test application time depends on the compression ratio and the length of codewords, and then propose a new Huffman-based coding method for achieving small test application time in a given test environment. The proposed coding method adjusts both of the compression ratio and the length of the cord words to the test environment. Experimental results show that the proposed method can archieve small test application time while keeping high compression ratio.

Test compression/decompression scheme using variable-length coding, e.g., Huffman coding, is efficient in reducing the test application time and the size of the storage on an LSI tester. In this paper, we propose a model of a decompressor with a buffer for variable-length coding and discuss its property. The embedded buffer allows the decompressor to operate at any input and output speed without a synchronizing feedback mechanism between an ATE and the decompressor. Moreover, we propose a method for reducing the size of the buffer embedded in the decompressor. Since the buffer size depends on the input order of test vectors, test vector reordering can reduce the buffer size. The proposed algorithm is based on fluctuations in buffered data for each test vector. Experimental results show a case where the ordering algorithm can reduce the size of the buffer by 97%.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper, we propose a response compression method based on Huffman coding. The proposed method guarantees zero-aliasing because faulty responses are mapped into code words, not just fault-free ones. Moreover, the method is independent of the fault model and the structure of a circuit-under-test, and uses only the knowledge of the fault-free responses corresponding to a given test input set. Experimental results of the compression ratio and the size of the encoder for the proposed method are presented.