Chihei Miura

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dblp:90/4037 · DBLP profile ↗

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4ranked-venue papers

0as first author

0since 2021 · last 1990

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

4 papers

Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation physical design	3	1984	Combine and top down block placement algorithm for hierarchical logic VLSI layout · DAC 1984 Automatic placement algorithms for high packing density V L S I · DAC 1983 A concurrent pattern operation algorithm for VLSI mask data · DAC 1981
Electronic design automation › logic synthesis logic optimization	1	1990	Logic Optimization Algorithm by Linear Programming Approach · DAC 1990
Electronic design automation logic synthesis	1	1990	Logic Optimization Algorithm by Linear Programming Approach · DAC 1990
Electronic design automation › physical design › placement › module placement block placement	1	1984	Combine and top down block placement algorithm for hierarchical logic VLSI layout · DAC 1984
Electronic design automation › physical design placement	1	1983	Automatic placement algorithms for high packing density V L S I · DAC 1983

Methods — techniques the papers use, named apart from their topics

linear programming · 0.0

Year	Publication	Venue	Position
1990	Logic Optimization Algorithm by Linear Programming Approach abstract A new logic synthesis algorithm for reducing the delay time with the least increase of gate is presented. This algorithm uses a linear programming approach and makes it possible for delay and gate optimization to be achieved simultaneously from the global point of view. Therefore, this new algorithm prevents the generation of redundant logic arising from the delay time improvement, which is a weakness of the conventional method. > Naohiro Kageyama, Chihei Miura, Tsuguo Shimizu	DAC	2
1984	Combine and top down block placement algorithm for hierarchical logic VLSI layout Tokinori Kozawa, Chihei Miura, Hidekazu Terai	DAC	2
1983	Automatic placement algorithms for high packing density V L S I Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno	DAC	5
1981	A concurrent pattern operation algorithm for VLSI mask data Tokinori Kozawa, Akira Tsukizoe, Jun'ya Sakemi, Chihei Miura, Tatsuki Ishii	DAC	4