In this paper we report the fully depleted CMOS/SO1 device design guidelines for low power applications.Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design.The differences and similarities are summarized.We believe this is the first such study to be reported.1.

Magnetic sensors are useful in applications such as magnetic read heads and non-contact current sensors. Ideally, a magnetic sensor should be easily integrated with its peripheral circuits. Experimental results indicate that it is possible to convert a conventional MOS transistor into a magnetic sensor by splitting the drain of the device into two. Such a device is attractive because the device is completely CMOS compatible. Integration of the sensor with electronic circuits can be easily achieved. However to realize such an integration, simulation model compatible with circuit simulators is essential. No such model has been reported. In this paper, we describe the development of a model for this split-drain MOS magnetic sensor which can be easily incorporated into popular circuit simulators such as SPICE. In developing this model, numerical simulations using symbolic mathematical tools are used to gain a physical understanding. The model is applicable for device operating in the linear region, and it is verified against experimental results.>

Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented.>

Based on an approximate solution to the nonlinear current continuity equation in the channel, an analytic non-quasi-static model for long-channel MOSFETs has been derived and implemented in SPICE. The model includes the large-signal transient and the small-signal AC analyses, although only the AC model is reported. Excellent agreement in simulation results has been achieved between this work and CODECS (a mixed device and circuit simulator). The CPU time required for this work is about twice as long as that for currently available quasi-static MOSFET models in SPICE.>

An analytic charge sheet capacitance model for short-channel MOSFETs is derived and implemented in SPICE. It is based on a surface potential formulation which computes the approximate surface potential without iterations. The DC current, charges, and their first and second derivatives are continuous under all operating regions. Equations for node charges are derived to guarantee charge conservation. Short-channel effects such as velocity saturation, channel-length modulation, and channel-side-fringing-field capacitances are included in the model equations. The model shows good agreement with the measured gate capacitance for long- and short-channel MOSFETs. The SPICE simulation of a ring oscillator using this model shows the significant variation of circuit performance due to the short-channel effects on capacitances.>

An analytic charge-conserving non-quasi-static (NQS) model is derived for long-channel MOSFETs and has been implemented in SPICE3. The model is based on approximate solutions to the transient current continuity equation, an analytic equations are derived for node charges using the charge-sheet formulation. The NQS effects in several test circuits, which include a pass transistor, a CMOS inverter chain, and a differential sample-hold circuit, are stimulated. Excellent agreements have been observed among this work, PISCES (2-D device simulation), the 1-D numerical simulation, the multiple lump model, and CODECS (a mixed device and circuit simulation). However, large differences have been observed between this work and conventional quasi-static (QS) models. The model computation time of this work implemented in SPICE3 is about 2-3 times larger than those of QS models (BSIM, Level-2 Meyer) in SPICE3.>