Complex scientific problems involving large volumes of data need a huge computing power.Memory bandwidth remains a key issue in high performance systems.This paper presents an originrd method of memory organization, based on serial multiport memory components, which allows simultaneous access to all ports without causing either cortfhct between them or suspension.The resulting process for information exchange gives a cost-effective realization of a data memory for vector processors.The memory bandwidth can be increased considerably in a modular manner, without practical implementation constraints.The information exchange on the serial links guarantees a continuous data flow and the reaching of a maximum yield of the pipeline, thus avoiding the step-by-step feeding of the pipeline operator.

This study has been carried out in order to determine cost-effective configurations of functional units for multiple-issue out-of-order superscalar processors. The trace-driven simulations were performed on the six integer and the fourteen floating-point programs from the SPEC 92 suite. We first evaluate the number of instructions allowed to be concurrently processed by the execution stages of the pipeline. We then apply some restrictions on the execution issue of different instruction classes in order to define these configurations. We conclude that five to nine functional units are necessary to exploit Instruction-Level Parallelism. An important point is that several data cache ports are required in a processor of degree 4 or more. Finally, we report on complementary results on the utilization rate of the functional units.

In out-of-order issue superscalar microprocessors, instructions must be buffered before they are issued. This buffer can be either unified (one buffer linked to all functional units) as in the P6, distributed among the units as in the PowerPC 620, or semi-unified (a few buffers each shared by several units) as in the MIPS R10000. Of course, the size of this buffer also plays a leading role in the performance of the processor. Intensive trace-driven simulations on the SPEC92 suite have been made in order to determine the best designs and relevant choices are pointed out according to the dispatch width of the processor.

A set of ultra high throughput (more than one Gigabits per second) serial links used as processor-memory network can lead to the starting up of a shared-memory massively parallel multiprocessor. The bandwidth of the network is far beyond values found in present shared-memory multiprocessor networks. To feed this network the memory must be serially multiported. Such a multiprocessor can actually be build with current technologies.

The design of M3S, an academic shared-memory multiprocessor, is described. The memory is divided into modules. Each processor (through its cache) has an access to each memory module only through a high-throughput private serial link. Each memory module has several serial ports that are connected, in parallel, to the memory. The data coherency is maintained by a hardware directory-based scheme. The interconnection network has no bottleneck since each processor has its private path to each memory module. The high bit rate of the serial links is the most important technical problem for the design of this prototype. Synchronous solutions have been chosen in the prototype because of their greater simplicity. The data rate on the serial links is 800 Mb/s. Choices made in order to realize this project with one memory module and sixteen processor modules are explained.>