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Ming-Chang Hsieh

dblp:90/4816 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 50% Embedded and real-time systems · 50%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
trace compression		 0.112008
An embedded infrastructure of debug and trace interface for the DSP platform · DAC 2008

Methods — techniques the papers use, named apart from their topics

trace compression · 0.1
YearPublicationVenuePosition
2008 An embedded infrastructure of debug and trace interface for the DSP platform
abstract
The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.
Ming-Chang Hsieh, Chih-Tsun Huang
 DAC1