The rapid development of LoRa and LoRaWAN received a wide interest in research in order to understand the performance of this technologies for various Internet of Things (IoT) applications. In this article, we propose an IoT system for smart buildings based on LoRa and LoRaWAN. The main aim of this system is monitoring the moisture of wood in buildings; specifically, in cultural heritage buildings. Monitoring uses wireless sensor nodes that are digitally controlled and low power. The wireless sensor node includes a moisture sensor that relies on a novel resistance measurement method which is developed and tested, including a new printed circuit board (PCB). The sensor comprises an LoRa communication module in order to be used as the end node of the proposed system. To complete the monitoring system, a cloud-based application was developed to provide remote visualization and control for all LoRa sensor nodes in a building. The proposed system is scalable and represents a practical solution for the early detection of wood moisture due to heavy rain, leaks, etc. The path loss is evaluated, showing that the proposed LoRa system can be applied for preservation of heritage buildings despite the attenuation of thick walls and complex architectural structures.

In this live demonstration we exploit the use of a serial link for fast asynchronous communication in massively parallel processing platforms connected to a DVS for real-time implementation of bio-inspired vision processing on spiking neural networks.

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging “neural spikes” among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

Event-based encoding reduces the amount of generated data while keeping relevant information in the measured magnitude. While this encoding is mostly associated with spiking neuromorphic systems, it can be used in a broad spectrum of tasks. The extension of event-based data representation to other sensors would provide advantages related to bandwidth reduction, lower computing requirements, increased processing speed and data processing. This work describes two event-based encoding procedures (magnitude-event and rate-event) for two sensors widely used in industry, especially for navigation in mobile systems: digital magnetic compass and ultrasonic distance sensor. Encoded data meet Address Event Representation (AER) format for further transmission, processing and visualization. Two encoding procedures and their associated AER conversion from sensor data are described, using an AVR microprocontroller to perform the task in real-time. Results are transmitted to a computer via USART, displayed and recorded using Matlab or jAER visualization tool. A comparison with classic transmitting and processing of sensor data is done to evaluate the convenience of the proposed encoding. Results show that data transmission bandwith can be reduced up to 95% under certain conditions, envisaging that pure or mixed regular/event-based data sensors are desirable for high speed transmission and low computer processing while keeping relevant information, which is highly desirable for mobile systems.

With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In numerous algorithms, it is also required to perform matrix multiplication repeatedly, where the result of a multiplication is further multiplied again. This work describes a versatile computation procedure and architecture: one of the matrices is stored in internal memory in its circulant form, then, a sequence of direct or transpose multiplications can be performed without timing penalty. The architecture proposes a RAM-ALU block for each matrix column, being connected in a systolic ring. The computation is propagated through internal RAM-ALU blocks. The architecture exploits local connections, minimizing delays. The system is described as an IP core, it is fully parameterisable to customize matrix size and data format when implementing. An$N\times N$matrix multiplication is performed in$\mathcal{O}(N^2)$clock cycles requiring$N$RAM-ALU blocks being$2N$in memory size. For a Virtex7 FPGA, clock runs at 340 MHz for 100$\times$100 and 290 MHz for 1000$\times$1,000 matrix size with 1 clock cycle per element multiplication.

Typically, hardware implemented neural networks are trained before implementation. Extreme learning machine (ELM) is a noniterative training method for single-layer feed-forward (SLFF) neural networks well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, which is very important in applications demanding on-chip training. This study proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the field-programmable gate array implementation for real-time detection of brain areas in electrode positioning during a deep brain stimulation surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a low-cost Spartan 6 device, making possible its real-time use in this application.

Extreme Learning Machine (ELM) is a noniterative training method suited for Single Layer Feed Forward Neural Networks (SLFF-NN). Typically, a hardware neural network is trained before implementation in order to avoid additional on-chip occupation, delay and performance degradation. However, ELM provides fixed-time learning capability and simplifies the process of re-training a neural network once implemented in hardware. This is an important issue in many applications where input data are continuously changing and a new training process must be launched very often, providing self-adaptation. This work describes a general SLFF-NN design environment to assist in the definition of neural network hardware implementation parameters including real-time ELM training. The software design environment uses initial user-provided input data with information about the type of problem: sample dataset and validated results, input fields, accuracy; and, together with simulation tools, recommends the optimum configuration for the neural topology and automatically generates synthesizable code for the hardware implementation tool. This is possible due to the design of parameter-dependent synthesis code and optimal hardware architecture design for both neural network and ELM training. Results show all the steps required to follow a successful design flow from the software tool to the final running device and, as an application example, the FPGA implementation for realtime detection of brain area in electrode positioning during a Deep Brain Stimulation (DBS) surgery is shown.

In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be step-by step formally transformed into the final specification of concurrent state machine model, closely related with VHDL description, suitable for a direct mapping in reconfigurable logic devices. In this paper it is proposed novel compact form of logic descriptions, directly based on event-oriented specification, where it is assumed that macrocells can be implicitly formed by synthesis tool as containing virtual T flip-flops.

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

Accurate weighting of pieces in different sorts of conveyor belts or articulated chains at fast speed is a key feature in many industrial processes. This paper presents a procedure to improve the performance, whether increasing speed or accuracy, of the load-cell-based weighting subsystem in a fruit sorting and grading machine to achieve an accuracy of /spl plusmn/1 gram at a speed of 20 fruits per seconds. The proposed solution includes a signal preprocessing based on a previous ARMA modeling of the weighting subsystem response plus a power line-noise removal and a simple sample averaging in the plateau. The procedure has been tested off-line using real signals acquired from a prototype machine.