Demo Data from EDBT 2026 / reviewers in the wild / expert
Joseph Nayfach-Battilana
dblp:90/5294
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 91% Performance modeling and evaluation · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing
power modeling |
0.1 | 1 | 2007 | Power model validation through thermal measurements · ISCA 2007 |
Energy-efficient computing › power-performance modeling
power model validation |
0.1 | 1 | 2007 | Power model validation through thermal measurements · ISCA 2007 |
Energy-efficient computing
thermal management |
0.1 | 1 | 2007 | Power model validation through thermal measurements · ISCA 2007 |
Methods — techniques the papers use, named apart from their topics
infrared thermography · 0.1genetic algorithm · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | SOI, interconnect, package, and mainboard thermal characterizationabstractThis paper presents an evaluation to determine the importance of the accurate thermal characterization for several elements of a semiconductor device. Specifically, it evaluates whether the decision to simplify or neglect to model metal interconnect density variation, Silicon-On-Insulator technology, the chip package, or the system main-board can effect the overall accuracy of a thermal model. In performing this evaluation, we motivate the need for more accurate thermal characterization of semiconductor devices. Through this analysis, designers are better able to understand how simplifications to their temperature models can effect the validity of design decisions derived from such models. Joseph Nayfach-Battilana, Jose Renau |
ISLPED | 1 |
| 2008 | Measuring power and temperature from real processorsabstractThe modeling of power and thermal behavior of modern processors requires challenging validation approaches, which may be complex and in some cases unreliable. In order to address some of the difficulties associated with the validation of power and thermal models, this document describes an infrared measurement setup that simultaneously captures run-time power consumption and thermal characteristics of a processor. We use infrared cameras with high spatial resolution (10 x 10 mum) and high frame rate (125 Hz) to capture thermal maps. Power measurements are obtained with a multimeter at a sampling rate of 1 K Hz. The synchronized traces can then be used in the validation process of possible thermal and power processor activity models. Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau |
IPDPS | 3 |
| 2007 | Power model validation through thermal measurementsabstractSimulation environments are an indispensable tool in the design, prototyping, performance evaluation, and analysis of computer systems. Simulator must be able to faithfully reflect the behavior of the system being analyzed. To ensure the accuracy of the simulator, it must be verified and determined to closely match empirical data. Modern processors provide enough performance counters to validate the majority of the performance models; nevertheless, the information provided is not enough to validate power and thermal models. In order to address some of the difficulties associated with the validation of power and thermal models, this paper proposes an infrared measurement setup to capture run-time power consumption and thermal characteristics of modern chips. We use infrared cameras with high spatial resolution (10x10μm) and high frame rate (125fps) to capture thermal maps. To generate a detailed power breakdown (leakage and dynamic) for each processor floorplan unit, we employ genetic algorithms. The genetic algorithm finds a power equation for each floorplan block that produces the measured temperature for a given thermal package. The difference between the predicted power and the externally measured power consumption for an AMD Athlon analyzed in this paper has less than 1 % discrepancy. As an example of applicability, we compare the obtained measurements with CACTI power models, and propose extensions to existing thermal models to increase accuracy. Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau |
ISCA | 2 |